• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.10a
• /
• pp.115-117
• /
• 2022

The electrical characteristics of the monolithic 3-dimensional static random access memory consisting of a feedback field-effect transistor (M3D-SRAM-FBFET) was investigated using technology computer-aided design (TCAD). The N-type FBFET and N-type MOSFET are designed with fully depleted silicon on insulator (FDSOI), and those are located at bottom and top tiers, respectively. For the M3D-SRAM-FBFET, as the supply voltage decreased from 1.9 V to 1.6 V, the reading on-current decreased approximately 10 times.

• Geophysics and Geophysical Exploration
• /
• v.19 no.3
• /
• pp.145-152
• /
• 2016

We used graphics processing units for an efficient time-domain 3D wave propagation modeling. Since graphics processing units are designed for massively parallel processes, we need to optimize the calculation and memory management to fully exploit graphics processing units. We focused on the memory management and examined the performance of programs with respect to the memory management methods. We also tested the effects of memory transfer on the performance of the program by varying the order of finite difference equation and the size of velocity models. The results show that the memory transfer takes a larger portion of the running time than that of the finite difference calculation in programs transferring whole 3D wavefield.

• Korean Journal of Materials Research
• /
• v.13 no.8
• /
• pp.497-502
• /
• 2003

Crystallographic characteristics and interfacial structures of $Al_2$$O_3$and $ZrO_2$dielectric films prepared by atomic layer chemical vapor deposition (ALCVD) were investigated at atomic scale by high-resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDS)/electron energy-loss spectroscopy (EELS) coupled with a field-emission transmission electron microscope. The results obtained from cross-sectional and plan-view specimens showed that the $Al_2$$O_3$film was crystallized by annealing at a high temperature and its crystal system might be evaluated as either cubic or tetragonal phase. Whereas the $ZrO_2$film crystallized during deposition at a low temperature of ∼$300^{\circ}C$ was composed of both tetragonal and monoclinic phase. The interfacial thickness in both films was increased with the increased annealing temperature. Further, the interfacial structures of X$ZrO_2$$O_3$and $ZrO_2$films were discussed through analyses of EDS elemental maps and EELS spectra obtained from the annealed films, respectively.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.4 no.3
• /
• pp.222-227
• /
• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• Journal of electromagnetic engineering and science
• /
• v.9 no.3
• /
• pp.152-158
• /
• 2009

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

• Journal of IKEEE
• /
• v.28 no.1
• /
• pp.110-115
• /
• 2024

This paper analyzed the V_th (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced V_th variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the V_th decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by V_fe proportional to the channel radius, leads to a greater reduction in V_th in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in V_th compared to the O/N/O structure, resulting in larger V_th variations with increasing tapering angles.

• Journal of information and communication convergence engineering
• /
• v.15 no.2
• /
• pp.117-122
• /
• 2017

Three-dimensional integrated circuits (3D ICs), starting with memory cubes, have entered the mainstream recently. The benefits many predicted in the past are indeed delivered, including higher memory bandwidth, smaller form factor, and lower energy. However, 3D ICs have yet to find their deployment in aerospace applications. In this paper we first present key design tools and methodologies for high performance, low power, and reliable 3D ICs that mainly target terrestrial applications. Next, we discuss research needs to extend their capabilities to ensure reliable operations under the harsh space environments. We first present a design methodology that performs fine-grained partitioning of functional modules in 3D ICs for power reduction. Next, we discuss our multi-physics reliability analysis tool that identifies thermal and mechanical reliability trouble spots in the given 3D IC layouts. Our tools will help aerospace electronics designers to improve the reliability of these 3D IC components while not degrading their energy benefits.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
• /
• v.24 no.2
• /
• pp.51-57
• /
• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Proceedings of the KOSOMBE Conference
• /
• v.1989 no.05
• /
• pp.39-43
• /
• 1989

In this paper, hierachical representation method with a 1-to-4 and 1-to-8 data structure is used to reconstruct the three-dimensional scene from two-dimensional cross sections provided by computed tomography with small memory computer system. To reduce the internal memory use, 2-D section is represented by quadtree, and 3-D scene is represented by octree. Octree is constructed by recursively merging consecutive quadtrees. This method uses 7/200 less memory than pointer type structure with all the case, and less memory up to 60.3% than linear octree with experimental data.

• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.774-777
• /
• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.