Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

The Analysis of Threshold Voltage Shift for Tapered O/N/O and O/N/F Structures in 3D NAND Flash Memory

3D NAND Flash Memory에서 Tapering된 O/N/O 및 O/N/F 구조의 Threshold Voltage 변화 분석

  • Jihwan Lee (Dept. of Electronics Engineering, Korea National University of Transportation) ;
  • Jaewoo Lee (Dept. of Electronics Engineering, Korea National University of Transportation) ;
  • Myounggon Kang (Dept. of Electronics Engineering, Korea National University of Transportation)
  • Received : 2024.02.28
  • Accepted : 2024.03.20
  • Published : 2024.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

This paper analyzed the Vth (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced Vth variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the Vth decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by Vfe proportional to the channel radius, leads to a greater reduction in Vth in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in Vth compared to the O/N/O structure, resulting in larger Vth variations with increasing tapering angles.

본 논문은 3D NAND Flash memory에서 tapering된 O/N/O(Oxide/Nitride/Oxide) 구조와 blocking oxide를 ferroelectric material로 대체한 O/N/F(Oxide/Nitride/Ferroelectric) 구조의 Vth(Threshold Voltage) 변화량을 분석했다. Tapering 각도가 0°일 때 O/N/F 구조는 O/N/O 구조보다 저항이 작고 WL(Word-Line) 상부와 WL 하부의 Vth 변화량이 감소한다. Tapering된 3D NAND Flash memory는 WL 상부에서 WL 하부로 내려갈수록 channel 면적이 감소하며 channel 저항이 증가한다. 따라서 tapering 각도가 증가할수록 WL 상부의 Vth가 감소하고 WL 하부의 Vth는 증가한다. Tapering된 O/N/F 구조는 channel 반지름 길이와 비례하는 Vfe로 인해 WL 상부의 Vth는 O/N/O 구조보다 더 감소한다. 또한 O/N/F 구조의 WL 하부는 O/N/O 구조보다 Vth가 증가하기 때문에 tapering 각도에 따른 Vth 변화량이 O/N/O 구조보다 더 증가한다.

Keywords

Acknowledgement

The research was supported by a grant from the 2023 program for visiting professors overseas in Korea National University of Transportation.

References

  1. J. G. Lee, W. J. Jung, J. H. Park, K. -H. Yoo and T. W. Kim, "Effect of the Blocking Oxide Layer with Asymmetric Taper Angles in 3-D NAND Flash Memories," IEEE J. Electron Devices Soc, vol.9, pp.774-777, 2021. DOI: 10.1109/JEDS.2021.3104843.
  2. Jaewoo Lee, Jongwon Lee, and Myounggon Kang. "The Analysis of Lateral Charge Migration at 3D-NAND Flash Memory by Tapering and Ferroelectric Polarization," Journal of IKEEE vol. 25, no.4, 2021. DOI: 10.7471/IKEEE.2021.25.4.770.
  3. P. Kumari, U. Surendranathan, M. Wasiolek, K. Hattar, N. P. Bhat and B. Ray, "Radiation-Induced Error Mitigation by Read-Retry Technique for MLC 3-D NAND Flash Memory," IEEE Trans Nucl Sci, vol.68, no.5, pp.1032-1039, 2021. DOI: 10.1109/TNS.2021.3052909.
  4. X. Yu et al. "LIAD: A Method for Extending the Effective Time of 3-D TLC NAND Flash Hard Decision," IEEE T COMPUT AID D, vol.42, no.5, pp.1705-1717, 2023. DOI: 10.1109/TCAD.2022.3191548.
  5. Y. Kong, M. Zhang, X. Zhan, R. Cao and J. Chen, "Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions," IEEE T COMPUT AID D, vol.39, no.11, pp.4042-4051, 2020. DOI: 10.1109/TCAD.2020.3025514.
  6. Dong Chan Lee, Jang Kyu Lee, and Hyungcheol Shin. "Machine learning model for predicting threshold voltage by taper angle variation and word line position in 3D NAND flash memory," IEICE Electron. Expr. vol.17, no.22 2020. DOI: 10.1587/elex.17.20200345
  7. K. Ko, J. K. Lee, H. Shin, "Variability-Aware Machine Learning Strategy for 3-D NAND Flash Memories," IEEE Trans Electron Devices, vol.67, no.4, pp.1575-1580, 2020. DOI: 10.1109/TED.2020.2971784.
  8. M. Raquibuzzaman, A. Milenkovic, B. Ray, "Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3-D NAND Flash Memory," IEEE Trans Electron Devices, vol.70, no.1, pp.70-75, 2023. DOI: 10.1109/TED.2022.3224420.
  9. Beomsu Kim, Myounggon Kang, "Optimal bias condition of dummy WL for sub-block GIDL erase operation in 3D NAND flash memory," Electronics. vol.11, no.17, pp.2738, 2022. DOI: 10.3390/electronics11172738
  10. D. Son, J. Park, H. Shin, "Investigation and compact modeling of hot-carrier injection for read disturbance in 3-D NAND flash memory," IEEE Trans Electron Devices, vol.67, no.7, pp. 2778-2784, 2020. DOI: 10.1109/TED.2020.2993772.
  11. S Choi, JK Jeong, Myounggon Kang, Y-h Song, "A novel structure to improve the erase speed in 3D NAND flash memory to which a cell-on-peri (COP) structure and a ferroelectric memory device are applied," Electronics. vol.11, no.13, pp.2038, 2022. DOI: 10.3390/electronics11132038
  12. J. -M. Sim, Myounggon Kang, Y. -H. Song, "A novel program operation scheme with negative bias in 3-D NAND flash memory," IEEE Trans Electron Devices, vol.68, no.12, pp.6112-6117, 2021. DOI: 10.1109/TED.2021.3121648.
  13. I Ham, Y Jeong, SJ Baik, Myounggon Kang, "Ferroelectric polarization aided low voltage operation of 3D NAND flash memories," Electronics. vol.10, no.1, pp.38, 2021. DOI: 10.3390/electronics10010038
  14. D. Kang et al. "Analysis of the current path for a vertical NAND flash cell with program/erase states," Semiconductor. Sci. Technol. 31 2016, 035011. DOI: 10.1088/0268-1242/31/3/035011
  15. Jihwan Lee, Jaewoo Lee, and Myounggon Kang. "Improvement of Current Path by Using Ferroelectric Material in 3D NAND Flash Memory," Journal of IKEEE vol.27, no.4, 2023. DOI: 10.7471/ikeee.2023.27.4.399
  16. S. Y. Chou and D. A. Antoniadis, "Relationship between measured and intrinsic transconductances of FET's," IEEE Trans Electron Devices, vol.34, no.2, pp.448-450, 1987. DOI: 10.1109/T-ED.1987.22942.
  17. U. M. Bhatt, S. K. Manhas, A. Kumar, M. Pakala and E. Yieh, "Mitigating the Impact of Channel Tapering in Vertical Channel 3-D NAND," IEEE Trans Electron Devices, vol.67, no.3, pp.929-936, 2020. DOI: 10.1109/TED.2020.2967869.
  18. Kim Y, Seon Y, Kim S, Kim J, Bae S, Yang I, Yoo C, Ham J, Hong J, Jeon J, "Analytical Current-Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance," Electronics. 2021. DOI: 10.3390/electronics10101177
  19. A. D. Gaidhane, G. Pahwa, A. Verma and Y. S. Chauhan, "Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor," IEEE Trans Electron Devices, vol.65, no.5, pp. 2024-2032, 2018. DOI: 10.1109/TED.2018.2813059.