• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2022년도 추계학술대회
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• pp.115-117
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• 2022

피드백 전계 효과 트랜지스터(feedback field-effect transistor; FBFET)로 구성된 모놀리식 3차원 정적 랜덤 액세스 메모리(monolithic 3-dimensional static random access memory; M3D-SRAM)에 대해 TCAD(technology computer-aided design) 프로그램을 사용하여 전기적 특성을 조사하였다. FBFET로 구성된 M3D-SRAM(M3D-SRAM-FBFET)는 FDSOI(fully depleted silicon on insulator) 구조의 N형 FBFET와 N형 MOSFET(metal oxide semiconductor field effect transistor)로 이루어져 있으며 각각 하부와 상부에 위치한다. M3D-SRAM-FBFET의 메모리 동작 시, 공급 전압이 1.9 V에서 감소함에 따라 읽기 전류가 낮아졌으며, 공급 전압이 1.6 V 일 때 읽기 전류가 약 10배 감소하였다.

• 지구물리와물리탐사
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• 제19권3호
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• pp.145-152
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• 2016

효율적인 시간 영역 3차원 파동 전파 모델링을 위해 그래픽 프로세서를 사용하였다. 그래픽 프로세서는 대규모 병렬 연산을 위한 프로세서로, 그래픽 프로세서를 효율적으로 이용하기 위해서는 계산 과정과 메모리 복사 과정을 최적화할 필요가 있다. 본 연구에서는 메모리 관리에 초점을 맞추고 메모리 관리 방법에 따라 그래픽 프로세서를 이용한 프로그램의 성능이 어떻게 달라지는지 확인하였다. 또한 유한 차분법 차수와 속도 모델의 크기를 변화시켜가며 메모리 복사가 프로그램 성능에 미치는 영향을 시험하였다. 그 결과 3차원 파동장 전체를 복사하는 프로그램에서 메모리 관리가 유한 차분법 계산보다 큰 비중을 차지함을 알 수 있었다.

• 한국재료학회지
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• 제13권8호
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• pp.497-502
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• 2003

Crystallographic characteristics and interfacial structures of $Al_2$$O_3$and $ZrO_2$dielectric films prepared by atomic layer chemical vapor deposition (ALCVD) were investigated at atomic scale by high-resolution transmission electron microscopy (HRTEM) and energy dispersive X-ray spectroscopy (EDS)/electron energy-loss spectroscopy (EELS) coupled with a field-emission transmission electron microscope. The results obtained from cross-sectional and plan-view specimens showed that the $Al_2$$O_3$film was crystallized by annealing at a high temperature and its crystal system might be evaluated as either cubic or tetragonal phase. Whereas the $ZrO_2$film crystallized during deposition at a low temperature of ∼$300^{\circ}C$ was composed of both tetragonal and monoclinic phase. The interfacial thickness in both films was increased with the increased annealing temperature. Further, the interfacial structures of X$ZrO_2$$O_3$and $ZrO_2$films were discussed through analyses of EDS elemental maps and EELS spectra obtained from the annealed films, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• Journal of electromagnetic engineering and science
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• 제9권3호
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• pp.152-158
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• 2009

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

• 전기전자학회논문지
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• 제28권1호
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• pp.110-115
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• 2024

본 논문은 3D NAND Flash memory에서 tapering된 O/N/O(Oxide/Nitride/Oxide) 구조와 blocking oxide를 ferroelectric material로 대체한 O/N/F(Oxide/Nitride/Ferroelectric) 구조의 V_th(Threshold Voltage) 변화량을 분석했다. Tapering 각도가 0°일 때 O/N/F 구조는 O/N/O 구조보다 저항이 작고 WL(Word-Line) 상부와 WL 하부의 V_th 변화량이 감소한다. Tapering된 3D NAND Flash memory는 WL 상부에서 WL 하부로 내려갈수록 channel 면적이 감소하며 channel 저항이 증가한다. 따라서 tapering 각도가 증가할수록 WL 상부의 V_th가 감소하고 WL 하부의 V_th는 증가한다. Tapering된 O/N/F 구조는 channel 반지름 길이와 비례하는 V_fe로 인해 WL 상부의 V_th는 O/N/O 구조보다 더 감소한다. 또한 O/N/F 구조의 WL 하부는 O/N/O 구조보다 V_th가 증가하기 때문에 tapering 각도에 따른 V_th 변화량이 O/N/O 구조보다 더 증가한다.

• Journal of information and communication convergence engineering
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• 제15권2호
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• pp.117-122
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• 2017

Three-dimensional integrated circuits (3D ICs), starting with memory cubes, have entered the mainstream recently. The benefits many predicted in the past are indeed delivered, including higher memory bandwidth, smaller form factor, and lower energy. However, 3D ICs have yet to find their deployment in aerospace applications. In this paper we first present key design tools and methodologies for high performance, low power, and reliable 3D ICs that mainly target terrestrial applications. Next, we discuss research needs to extend their capabilities to ensure reliable operations under the harsh space environments. We first present a design methodology that performs fine-grained partitioning of functional modules in 3D ICs for power reduction. Next, we discuss our multi-physics reliability analysis tool that identifies thermal and mechanical reliability trouble spots in the given 3D IC layouts. Our tools will help aerospace electronics designers to improve the reliability of these 3D IC components while not degrading their energy benefits.

• 한국전자파학회지:전자파기술
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• 제24권2호
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1989년도 춘계학술대회
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• pp.39-43
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• 1989

In this paper, hierachical representation method with a 1-to-4 and 1-to-8 data structure is used to reconstruct the three-dimensional scene from two-dimensional cross sections provided by computed tomography with small memory computer system. To reduce the internal memory use, 2-D section is represented by quadtree, and 3-D scene is represented by octree. Octree is constructed by recursively merging consecutive quadtrees. This method uses 7/200 less memory than pointer type structure with all the case, and less memory up to 60.3% than linear octree with experimental data.

• 전기전자학회논문지
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• 제25권4호
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• pp.774-777
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• 2021

본 논문은 Charge Trap Flash using Ferroelectric(CTF-F) 구조를 가진 3D NAND Flash Memory gate controllability에 대해 분석했다. Ferroelectric 물질인 HfO₂는 polarization 이외에도 high-k 라는 특징을 가진다. 이러한 특징으로 인해 CTF-F 구조에서 gate controllability가 증가하고 Bit Line(BL)에서 on/off 전류특성이 향상된다. Simulation 결과 CTF-F 구조에서 String Select Line(SSL)과 Ground Select Line(GSL)의 채널길이는 100 nm로 기존 CTF 구조에 비해 33% 감소했지만 거의 동일한 off current 특성을 확인했다. 또한 program operation에서 channel에 inversion layer가 더 강하게 형성되어 BL을 통한 전류가 약 2배 증가한 것을 확인했다.