• Journal of Welding and Joining
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• v.34 no.3
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• pp.40-46
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• 2016

The digital controlled SMA welding power source having the hot start current and short circuit waveform control was developed. The inverter power controller was used an analog circuit and the short circuit waveform controller was developed using a 8-bit MCU. For the evaluation of the developed SMA welding power source it were compared with a domestic welding power sources. Using the high titanium oxide type and low hydrogen type electrodes, the characteristics of hot start and short circuit was evaluated. Developed SMA welding power source shows good start performance. Also, arc stability and low current weldability were improved by the short circuit waveform control.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2006.05a
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• pp.407-409
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• 2006

This paper presents the methods of designing the control circuits for a Class D amplifier to have a peak performance. The proposed approach is based on the three functional components - a carrier generator, a feedback circuit and a dead-time circuit. First the analog signal is applied to the controller, which outputs the 3 level PWM waveform. The controller used for this experiment is made of the operational amplifier and the logic circuit. The experimental results show that the control circuit performs with satisfaction and its output is proportional to input audio signal, providing a satisfactory 3 level PWM pattern. From this design methodology, by implementing a proposed control circuit we can achieve the efficient Class D amplifier using the half-bridge, full-bridge or push-pull topology at the output stage.

• Journal of information and communication convergence engineering
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• v.15 no.2
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• pp.112-116
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• 2017

In this work, we demonstrated a low noise and high linearity low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with novel active bias circuit for LTE applications. The device technology used in this work relies on a process involving a $0.25-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (PHEMT). The LNA MMIC with a novel active bias circuit has a small signal gain of $19.7{\pm}1.5dB$ and output third order intercept point (OIP3) of 38-39 dBm in the frequency range 1.75-2.65 GHz. The noise figure (NF) is less than 0.58 dB over the full bandwidth. Compared with the characteristics of the LNA MMIC without using the novel active bias circuit, the OIP3 is improved about 2-3 dBm. The small signal gain and NF showed no significant change after using the active bias circuit. The novel active bias circuit indeed improves the linearity performance of the LNA MMIC without degradation.

• ETRI Journal
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• v.19 no.2
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• pp.35-47
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• 1997

A power amplifier operating at 3.3 V has been developed for CDMA/AMPS dual-mode cellular phones. It consists of linear GaAs power MESFET's, a new gate bias control circuit, and an output matching circuit which prevents the drain terminal of the second MESF from generating the harmonics. The relationship between the intermodulation distortion and the spectral regrowth of the power amplifier has been investigated with gate bias by using the two-tone test method and the adjacent channel leakage power ratio (ACPR) method of CDMA signals. The dissipation power of the power amplifier with a gate bias control circuit is minimized to below 1000 mW in the range of the low power levels while satisfying the ACPR of less than -26 dBc for CDMA mode. The ACPR of the power amplifier is measured to be -33 dBc at a high output power of 26 dBm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.1
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• pp.77-83
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• 2011

In this thesis, 50W Doherty amplifier was designed and implemented for Beyond 3G's repeater and base-station. Auxiliary amplifier of doherty amplifier was implemented by Gate bias control circuit. Though gate bias control circuit solved auxiliary's bias problem, output characteristics of doherty amplifier was limited. To enhance the output characteristic relativize Drain control circuit And To improve power efficiency make 3-way Doherty power amplifier. therefore, 3-way GDCD (Gate and Drain bias Control Doherty) power amplifier is embodied to drain bias circuit for General Doherty power amplifier. The 3-way GDCD power amplifier composed of matching circuit with chip capacitor and micro strip line using FR4 dielectric substance of specific inductive capacity(${\varepsilon}r$) 4.6, dielectric substance height(H) 30 Mills, and 2.68 Mills(2 oz) of copper plate thickness(T). Experiment result satisfied specification of amplifier with gains are 57.03 dB in 2.11 ~ 2.17 GHz, 3GPP frequency band, PEP output is 50.30 dBm, W-CDMA average power is 47.01 dBm, and ACLR characteristics at 5MHz offset frequency band station is -40.45 dBc. Especially, 3-way DCHD power amplifier showed excellence efficiency performance improvement in same ACLR than general doherty power amplifier.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.151-161
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• 2013

An active power factor correction (PFC) circuit is presented which employs a newly proposed input voltage sensor-less control technique operated in continuous conduction mode (CCM) and critical conduction mode (CRM). The conventional PFC circuit with input voltage sensor-less control technique degrades the power factor (PF) under the light load condition due to DCM operation. In the proposed PFC circuit, the switching frequency is basically 70KHz in CCM operation. In light load condition, however, the PFC circuit operates in CRM and the switching frequency is increased up to 200KHz. So CCM/CRM operation of the PFC circuit alleviates the decreasing of the PF in light load condition. The proposed PFC controller IC has been implemented in a $0.35{\mu}m$ BCDMOS process and a 240W PFC prototype is built. Experimental results shows the PF of the proposed PFC circuit is improved up to 10% from the one employing the conventional CCM/DCM dual mode control technique. Also, the PF is improved up to 4% in the light load condition of the IEC 61000-3-2 Class D specifications.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.2
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• pp.91-97
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• 2000

Tn this paper, a novel control circuit applicable to the error sensor loop block in the feedforward linearizer system is proposed. The proposed control circuit is applied to the error sensor loop block, where in the 11dB power range, it operates stably, and makes main carrier signals to be eliminated more than 40dB below 3$\^$rd/ order IM level. In the operating point, the amplitude control error is 0.05∼0.12dB, and the phase control error is smaller than 0.02。. It is verified theoretically as well as experimentally that the control circuit can precisely compensate the variation of nonlinear characteristics in a high power amplifier, due to the variations of input power, operating temperature, humidity and the other system environments.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.32-37
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• 2007

A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.959-965
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• 2019

In this paper, we design a low noise amplifier to support ka-band satellite communication systems using 65-nm RFCMOS process. The proposed low noise amplifier is designed with high-gain mode and low-gain mode, and is designed to control the gain according to the magnitude of the input signal. In order to reduce the power consumption, the supply voltage of the entire circuit is limited to 1 V or less. We proposed the gain control circuit that consists of the inverter structure. The 3D EM simulator is used to reduce the size of the circuit. The size of the designed amplifier including pad is $0.33mm^2$. The fabricated amplifier has a -7 dB gain control range in 3 dB bandwidth and the reflection coefficient is less than -6 dB in high gain mode and less than -15 dB in low gain mode.