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A Highly Linear and Efficient DMB CMOS Power Amplifier with Adaptive Bias Control and 2nd Harmonic Termination circuit  

Choi, Jae-Won (Information and Telecommunication Engineering, Soongsil University)
Seo, Chul-Hun (Information and Telecommunication Engineering, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea TC / v.44, no.1, 2007 , pp. 32-37 More about this Journal
Abstract
A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.
Keywords
Adaptive bias; harmonic termination; power added efficiency (PAE); CMOS PA; DMB;
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