• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.257-259
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• 2019

We have investigated the electrical coupling in a 3D monolithic NOR gate structure using TCAD simulation. The electrical coupling of 3D monolithic NOR gate can be caused by the transistor located in the upper/lower or diagonal transistors. The drain current of the upper layer NMOSFET is the same when the voltage of PgateB is 0 V and 1 V. It has been confirmed that the electrical coupling in the diagonal direction does not affect the device characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.481-482
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• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.514-516
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• 2018

We have investigated the effect of interface trap charge on the characteristics of a monolithic 3D inverter by TCAD simulation. The interface trap charge affects the variation of the threshold voltage and threshold voltage. also The interface trap charge affects the IN/OUT characteristics of the monolithic 3D inverter.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.115-117
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• 2022

The electrical characteristics of the monolithic 3-dimensional static random access memory consisting of a feedback field-effect transistor (M3D-SRAM-FBFET) was investigated using technology computer-aided design (TCAD). The N-type FBFET and N-type MOSFET are designed with fully depleted silicon on insulator (FDSOI), and those are located at bottom and top tiers, respectively. For the M3D-SRAM-FBFET, as the supply voltage decreased from 1.9 V to 1.6 V, the reading on-current decreased approximately 10 times.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.4
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• pp.462-470
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• 2015

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.200-201
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• 2017

This paper introduces the SPICE simulation results of 3D sequential inverter considering electrical coupling. TCAD data and the SPICE data are compared to verify that the electrical coupling is well considered by using BSIM-IMG for the upper NMOS and LETI-UTSOI model for the lower PMOS. When inter layer dielectric is small, it is confirmed that electrical coupling is well reflected in the top transistor $I_{ds}-V_{gs}$ characteristics according to the change of the bottom transistor gate voltage.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.