• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.145-150
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• 2016

The capability of accurate positioning and tracking is necessary to implement an unmanned autonomous driving system. The moving-baseline GPS Technique is a promising candidate to mitigate positioning errors of conventional GPS system. It provides accurate positioning data based on the phase difference between received signals from multiple GPS antennas mounted on the same platform. In this paper, we propose a dual-band dual-circularly-polarized antenna suitable for the moving-baseline GPS. The proposed antenna operates at GPS L1 and L2 bands, and fed by the side of the antenna instead of the bottom. The antenna is firstly designed by calculating theoretical values of key parameters, and then optimized by means of 3D full-wave simulation software. Simulation and measurement results show that the optimized antenna offers 6.1% and 3.7% bandwidth at L1 and L2, respectively, with axial ratio bandwidth of more than 1%. The size of the antenna is $73mm{\times}73mm{\times}6.4mm$, which is small and low-profile.

• Journal of Advanced Navigation Technology
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• v.22 no.2
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• pp.148-153
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• 2018

This paper proposes a single-input multiple-output (SIMO) self-resonant wireless power transmission system for transmitting power to multiple receivers and the characteristics are simulated and measured. A 600 mm diameter transmission single loop, a 600 mm diameter helical transmission resonant coil, an external diameter 900 mm planar spiral reception resonant coil, and an $80{\times}60mm^2$ flat plate square coil as a receiver are used to form a wireless power transmission system 600 mm away with the table structure. For optimal characteristics, the wireless power transmission coils are designed by EM simulation and equivalent circuit analysis, and the characteristics are simulated and measured. The variation of the efficiency with distance from the center of the spiral resonant coil is analyzed and the measured efficiency is 57% for one receiver and for the two receivers, the efficiency is 37% for each receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.12
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• pp.1237-1244
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• 2015

A gerotor can be manufactured in a miniature size because it has a high discharge per cycle and a simple structure. Gerotors are widely used for the lubrication oil of an engine and as the hydraulic source of an automatic transmission. Recently, improvements in fuel efficiency and noise reduction have come to the fore in the automobile industry, and it has been necessary for better fuel efficiency to continuously improve the flow rate and noise of internal gear pumps through the optimal design of the gerotor and port shape. In this study, gerotors were generated based on the equations derived for a lobe shape with multiple profiles (ellipse 1-elliptical involute-ellipse 2). The ranges of the design parameters were considered to prevent a cusp and loop. In addition, the optimal lobe shape was obtained by determining the influence of the lobe shape on the performances (flow rate, irregularity, etc.), according to the values of the design parameters.

• Korean Chemical Engineering Research
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• v.49 no.5
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• pp.565-570
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• 2011

In this paper, the analytical tuning rules of the proportional-integral-derivative (PID) controller have been derived for a broad class of stable, integrating, and unstable processes without time delay. On the basis of the renowned internal model control (IMC) design principles and the two-degree-of-freedom (2DOF) control structure, the proposed method can be effectively used for obtaining the enhanced performances of both the disturbance rejection as well as the set-point tracking problems, since the design scheme is simple, straightforward, and can be easily implemented in the process industry. Several processes without time delay are employed to demonstrate the improved closed-loop performance of the proposed controller design in compared with the other well-known design methods in terms of the same degree of robustness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.5
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• pp.435-443
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• 2009

In this paper, we propose a microstrip slot antenna that works in Bluetooth, Zigbee, WiMAX and WLAN frequency bands($2.4{\sim}5.825\;GHz$). To get the wide bandwidth from the microstrip antenna proposed, we insert a pair of parastic strips along the feed line on the FR-4 dielectric substance(${\varepsilon}_r=4.8$). Furthermore, a simple geometrical rotation with quadrilateral slot is designed to maximize the bandwidth and to gain a wider frequency band than the conventional rectangular slot antenna. A additional design of the loop type is added to a cactus-shaped patched for 2.4 GHz ISM frequency band. The total measured bandwidth of the antenna is from 2.4 GHz to 6 GHz and the maximum gains of the antenna are 3.82 dBi, 4.48 dBi, 6.41 dBi and 6.65 dBi at the frequencies of 2.4 GHz, 3.5 GHz, 5.25 GHz and 5.77 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.681-689
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• 2010

We will demonstrate a novel topology for the feedforward amplifier. This amplifier does not use a delay element thus providing an efficiency enhancement and a size reduction by employing a distributed element negative group delay circuit. The insertion loss of the delay element in the conventional feedforward amplifier seriously degrades the efficiency. Usually, a high power co-axial cable or a delay line filter is utilized for a low loss, but the insertion loss, cost and size of the delay element still acts as a bottleneck. The proposed negative group delay circuit removes the necessity of the delay element required for a broadband signal suppression loop. With the fabricated 2-stage distributed element negative group delay circuit with -9 ns of total group delay, a 0.2 dB of insertion loss, and a 30 MHz of bandwidth for a wideband code division multiple access downlink band, the feedforward amplifier with the proposed topology experimentally achieved a 19.4 % power added efficiency and a -53.2 dBc adjacent channel leakage ratio with a 44 dBm average output power.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.12
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• pp.6558-6564
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• 2013

As the average indicator for amount of water flowing in any cross section of a river, the mean discharge has been reported to be a very important factor for examining water circle constructions in a river basin, the design and construction of a hydraulic structure, and water front area use and management. The stage-discharge curve based on discharge and stage data measured in a normal season were basically derived. Using this derivation, the necessary discharge data was obtained. The values produced in this manner corresponded to the measured data in a uniform flow state well, but showed limited accuracy in a flood season (unsteady flow). In the present paper, the mean velocity in unsteady flow conditions, which exhibited loop form properties, was estimated using the new mean velocity formula derived from Chiu's 2-D velocity. The results of RMSE and Polar graph analyses showed that the proposed equation exhibited approximately nineteen times the accuracy compared to the Manning and Chezy equations.