• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.37-50
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• 2009

Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.

• Journal of IKEEE
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• v.27 no.1
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• pp.65-70
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• 2023

More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and various CNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductor chip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discusses a methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAM or CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM and compare its performance with the conventional MOSFET SRAM and CNTFET SRAM.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of IKEEE
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• v.11 no.4
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• pp.129-136
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• 2007

In this paper, a simple but effective Dataline Redundancy Circuit (DRC) is proposed for a dual-port 1T-SRAM embedded in Display ICs. The DRC designed in the dual-port $320{\times}120{\times}18$-bit 1T-SRAM is verified in a 0.18-um CMOS 1T-SRAM process. In the DRC, because its control logic circuit can be implemented by a simple Shift Logic Circuit (SLC) with only an inverter and a NAND that is much simpler than the conventional, it can be placed in a pitch as narrow as a bit line pair. Moreover, an improved version of the SLC is also proposed to reduce its worst-case delay from 12.3ns to 5.9ns by 52%. By doing so, the timing overhead of the DRC can be hidden under the row cycle time because switching of the datalines can be done between the times of the word line setup and the sense amplifier setup. The area overhead of the DRC is estimated about 7.6% in this paper.

• Journal of Sensor Science and Technology
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• v.33 no.3
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• pp.152-157
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• 2024

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.7-17
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• 2010

In this paper, an innovative low-power SRAM based on 4-transistor latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. Moreover, the design reduces the leakage current in the memory cells. The proposed SRAM has been demonstrated through 16-kbit test chip fabricated in a 0.18-${\mu}m$ CMOS process. It shows 17.5 ns access at 1.8-V supply while consuming dynamic power of $87.6\;{\mu}W/MHz$ (for read cycle) and $70.2\;{\mu}W/MHz$ (for write cycle). Compared with those of the conventional 6-transistor SRAM, it exhibits the power reduction of 30 % (read) and 42 % (write) respectively. Silicon measurement also confirms that the proposed SRAM achieves nearly 64 % reduction in the total standby power dissipation. This novel SRAM might be effective in realizing low-power embedded memory in future mobile applications.

• Journal of the Korean Society of Industry Convergence
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• v.24 no.1
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• pp.69-77
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• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.