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http://dx.doi.org/10.21289/KSIC.2021.24.1.69

A Study on Improvement of Low-power Memory Architecture in IoT/edge Computing  

Cho, Doosan (Dept. of Electrical & Electronic Engineering, Sunchon National University)
Publication Information
Journal of the Korean Society of Industry Convergence / v.24, no.1, 2021 , pp. 69-77 More about this Journal
Abstract
The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.
Keywords
Data mapping; architecture graph; architecture; system performance; low power;
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