• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Mass Spectrometry Letters
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• v.9 no.1
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• pp.37-40
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• 2018

Farinomalein is a maleimide-bearing compound well known for its anti-fungal activity. In the present study, synthesis of farinomalein is achieved via Stobbe condensation followed by Haval-Argade contrathermodynamic rearrangement. Kinetically driven Stobbe condensation followed by condensation with beta-alanine reveals formation of two isomers of farinomalein. This article describes application of LC-MS/MS in structure elucidation of farinomalein 1 and its isomers 2 and 3 encountered in its synthesis. The proposed distinct fragmentation pathway is supported by rational organic reaction mechanism. These fragmentation pathways are significant for analytical method development of farinomalein in near future. The structures of farinomalein 1 and its isomers 2 and 3 have been assigned undisputedly.

• Journal of Plant Biotechnology
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• v.6 no.1
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• pp.55-61
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• 2004

Callus induction and somatic embryogenesis are fundamental to cotton tissue culture biotechnology. An efficient protocol for callus induction, somatic embryogenesis and their maturation have been developed to regenerate plantlets from cotton (Gossypium hirsutum L.) variety coker 312. Embryogenic callus was initiated from hypo-cotyl region that was used as an explant at seedling stage when it was about 7-8 days old. Callus induction was achieved through culturing hypocotyls (5-7mm) on $MS_{1a} medium supplemented with 2,4-D (0.1 mg/L) and KT (0.5 mg/L) for six weeks. A friable, colorless, bulky and well proliferating callus becomes greenish with the addition of NAA (2.0 mg/L), ZT (0.1 mg/L) and removal of 2,4-D (M $S_{1b}$) cultured for two weeks then again transferred to $MS_{1a}. 2,4-dichlorophenoxyacetic acid (2,4-D) promoted the proliferation of embryogenic callus, but had a negative effect on the differentiation and germination of somatic embryos. ZT (0.1mg/L) and activated charcoal (2g/L), both hormones play an important role in differentiation and germination of somatic embryos in hypocotyls derived embryogenic callus but in case of cotton, such a capability have been observed on MS medium with 1.92 g/L $KNO_3$, but it is considered to attain somewhat more improvement. High embryogenesis frequency was achieved through nutrient deficient stress treatment. The frequency of globular embryogenesis (two-three folds) was achieved when well proliferating callus was (from $MS_{1a}$ media) cultured on MS (1/5 strength) medium for four weeks. Here the development of anthocyanins is the best indicator for somatic embryogenesis. However, when embryoid callus was cultured on MS (full strength) medium, the globular embryos were developed into normal plantlets immediately. In this procedure 27.49% cotyledenary embryos were developed. Of that 70% cotyledenary embryos were developed not only into normal plantlets but rooted simultaneously, when cultured on MS (with 0.05 mgg/L giberrelic acid) medium. So complete plants could be regenerated through somatic embryogenesis from hypocotyl explants within 6 months.s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• Proceedings of the Korean Society of Disaster Information Conference
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• 2022.10a
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• pp.203-204
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• 2022

본 논문에서는 공공기관에서 안전보건경영시스템으로 KOSHA-MS를 구축하여 유지하고 있습니다. 2022년 1월 27일 시행된 중대재해처벌법에 대한 준비와 대책을 수립하고 있으며, 공공기관 안전활동 수준평가, 공공기관 안전관리등급제 등 여러 평가를 받고 있습니다. 이에 안전보건경영시스템(KOSHA-MS) 규정에 중대재해처벌법과 관련법규의 연계와 공공기관 안전활동 수준평가, 공공기관 안전관리등급제까지 연계 방안을 연구하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.54-63
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• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of agriculture & life science
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• v.44 no.6
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• pp.39-44
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• 2010

An efficient method for the rapid propagation of Smilax china from axillary buds was established. Plants with thick leafage were selected from Korea native S. china population. Axillary buds of S. china collected from selected plant and were cultured in various culture media (2MS, MS, 1/2MS, WPM, B5 and SH medium). Shoot was induced from axillary bud on MS basal medium after 4 weeks of culture. 1/2MS medium showed a higher growth rate than those of the others, while the lowest shoot growth was obtained in 2MS medium. Among the sucrose concentrations, 5% sucrose was the optimum level for shoots growth from axillay buds. Among cytokinins, $0.5mgL^{-1}$ 6-benzylaminopurine (BAP) treatment showed the best performance on shoot multiplication, yielding average shoot multiplication forming about 2.4. Rooting was induced directly near the base of the shoot on 1/2MS medium containing with three-auxins ${\alpha}-napthalene$ acetic acid (NAA), indole acetic acid (IAA) and ${\beta}-indolebutyric$ acid (IBA) (0.5 and $1.0mgL^{-1}$). The $1.0mgL^{-1}$ IBA treatments induced earliest rooting with maximum of root number and root growth. These rooted plantlets were successfully transferred to pots for 4 weeks hardening process, and were transferred to soil with above 90% survival rate.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.