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A 10b 200MS/s 75.6mW $0.76mm^2$ 65nm CMOS Pipeline ADC for HDTV Applications  

Park, Beom-Soo (Dept. of Electronic Engineering, Sogang University)
Kim, Young-Ju (Dept. of Electronic Engineering, Sogang University)
Park, Seung-Jae (Dept. of Electronic Engineering, Sogang University)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.3, 2009 , pp. 60-68 More about this Journal
Abstract
This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.
Keywords
RNMC; multipath; 65nm; CMOS; ADC;
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1 L. Sumanen, M. Waltari, and K. A. I. Halonen, "A 10-bit 200-MS/s CMOS parallel pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1048-1055, July 2001   DOI   ScienceOn
2 S. C. Lee, Y. D. Jeon, K. D. Kim, J. K. Kwon, J. D. Kim, J. W. Moon, and W. Y. Lee, "A 10b 205MS/s 1$mm^2$ 90nm CMOS pipeline ADC for flat-panel display applications," in ISSCC Dig. Tech Papers, Feb. 2007, pp. 458-615   DOI
3 J. Li and U. K. Moon, "A 1.8-V 67-mW 10-bit 100-MS/s Pipelined ADC Using Time-Shifted CDS Technique," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1468-1476, Sept. 2004   DOI   ScienceOn
4 B. R. Gregoire and U. K. Moon, "An Over-60dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp with 30dB Loop Gain," in ISSCC Dig. Tech Papers, Feb. 2008, pp. 540-541   DOI
5 K W. Hsueh, Y. K Chou, Y. H. Tu, Y. F. Chen, Y. L. Yang, and H. S. Li, "A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nrn CMOS," in ISSCC Dig. Tech Papers, Feb. 2008, pp. 546-547
6 http://www.itrs.net
7 J. Li, G. Manganaro, M. Courcy, B. M. Min, L. Tomasi, A. Alam, and R. Taylor, "A 10b 170MS/s CMOS pipelined ADC featuring 84dB SFDR without calibration," in Symp. VLSI Circuits Dig. Tech Papers, June 2006, pp. 226-227   DOI
8 M. Boulernnakher, E. Andre, J. Roux, and F. Paillardet, "A 1.2V 4.5mW 10b 100MS/s pipeline ADC in a 65nm CMOS," in ISSCC Dig. Tech Papers, Feb. 2008, pp. 250-251   DOI
9 R. Eschauzier and J. Huijsing, "Frequency Compensation Techniques for Low-Power Operational Amplifiers", Kluwer Academic Publisher, pp. 160-166, 1995
10 S. C. Lee, K. D. Kim, J. K. Kwon, J. D. Kim, and S. H. Lee., "A 10bit 400MS/s 160mW 0.13um CMOS Dual-Channel Pipeline ADC Without Channel Mismatch Calibration," IEEE J. Solid-State Circuits, vol. 41, No.7, pp. 1596-1605, July 2006   DOI   ScienceOn
11 B. Heroes, J. Bjorosen, T. N. Andersen, A, Vinje, H. Korsvoll, F. Telsto, A. Briskemyr, C. Holdo, and O. Moldsvor, "A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13um CMOS," in ISSCC Dig. Tech Papers, Feb. 2007, pp. 462-463
12 G. C. Ahn, P. K Hanumolu, M. G. Kim, S. Takeuchi, T. Sugimoto, K. Hamashita K. Takasuka, G. C. Temes, and U. K. Moon., "A 12b 10MS/s Pipelined ADC Using Reference Scaling," in Symp. VLSI Circuits Dig. Tech Papers, June 2006, pp. 220-221   DOI
13 D. J. Huber, R. J. Chandler, and A. A. Abidi, "A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS," in ISSCC Dig. Tech Papers, Feb. 2007, pp. 454-455   DOI
14 C. C. Hsu, C. C. Huang, Y. H. Lin, and C. C. Lee, "A 10b 200MS/s Pipelined Folding ADC," in Proc. European Solid-State Orcuits Conference, Sept. 2007, pp. 151-154   DOI
15 B. Hernes, A. Briskemyr, T. N. Andersen, F. Telsto, T. E. Bonnerud, and O. Moldsvor, "A 1.2V 220MS/s 10b pipeline ADC implemented in 0.13um digital CMOS," in ISSCC Dig. Tech Papers, Feb. 2004, pp. 256-257
16 S. C. Lee, G. H Kim, J. K. Kwon, J. D. Kim, and S. H. Lee, "Offset and Dynamic Gain -Mismatch Reduction Techniques for 10b 200MS/s Parallel Pipeline ADCs," in Proc. European Solid-State Circuits Conference, Sept. 2005, pp. 531-534
17 J. Li, R. Leboeuf, M. Courcy, and G. Manganaro, "A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration," in Proc. CICC, Sept. 2007, pp. 317-320   DOI