• The KIPS Transactions:PartB
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• v.12B no.6 s.102
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• pp.637-646
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• 2005

Most of the multimedia contents for DBM services art provided as MPEG-2 bit streams. However, they have to be transcoded to H.264 bit streams for practical services because the standard video codec for DMB is H.264. The existing transcoder architecture is Cascaded Pixel-Domain Transcoding Architecture, which consists of the MPEG-2 dacoding phase and the H.264 encoding phase. This architecture can be easily implemented using MPEG-2 decoder and H.264 encoder without source modifying. However. It has disadvantages in transcoding time and DCT-mismatch problem. In this paper, we propose two kinds of transcoder architecture, DCT-OPEN and DCT-CLOSED, to complement the CPDT architecture. Although DCT-OPEN has lower PSNR than CPDT due to drift problem, it is efficient for real-time transcoding. On the contrary, the DCT-CLOSED architecture has the advantage of PSNR over CPDT at the cost of transcoding time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.936-944
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• 2003

In this paper, we propose an AND/XOR-based technology mapping method for field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem to decompose a given Boolean circuit. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as error detecting/correcting, data encryption/decryption, and arithmetic circuits, efficiently. We conduct experiments using MCNC benchmark circuits. When using the proposed approach, the number of CLBs (configurable logic blocks) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), total equivalent gate counts are reduced by 65.5 %, maximum combinational path delay is reduced by 56.7 %, and maximum net delay is reduced by 80.5 % compared to conventional methods.

• Journal of Internet Computing and Services
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• v.16 no.3
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• pp.33-41
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• 2015

In this paper, the simplification procedure of Karnaugh Map, which is essential to design digital logic circuits, was implemented as web-based educational Java applets. The learners will be able to experience interesting learning process by executing the proposed Java applets. In addition, since the proposed Java applets were designed to contain educational technologies by step-by-step procedure, the maximization of learning efficiency can be obtained. The learners can make virtual experiments on the simplification of digital logic circuits by clicking on some buttons or filling out some text fields. Furthermore, the Boolean expression and its schematic diagram occurred in the simplification process will be displayed on the separate frame so that the learners can learn effectively. The schematic diagram enables them to check out if the logic circuit is correctly connected or not. Finally, since the simplification algorithm used in the proposed Java applet is based on the modified Quine-McCluskey minimization technique, the proposed Java applets will show more encouraging result in view of learning efficiency if it is used as assistants of the on-campus offline class.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.5
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• pp.1225-1231
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• 2018

FPGA-based system development is being developed as a form of outsourcing that shortens the development time and reduces the cost. Through the process, the risk of letting the hardware Trojan, which causes malfunctions, seep into the system also increases. Various detection methods are proposed for the issue; however, such type of hardware Trojans is inserted by modifying a bitstream directly and therefore, it is hard to detect with the suggested methods. To detect the type of hardware Trojans, it is essential to reverse-engineer the electric circuit implemented by bitstream to a distinguishable level. Specifically, it is important to reverse-engineer the routing information of the circuit that can identify the input-output flow of the signal. In this paper, we analyze the BIL bitstream reverse-engineering tool-chain that uses the algorithm, which retrieves the routing information from FPGA bitstream, and suggest the method to improve the tool-chain.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.87-94
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• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.8
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• pp.318-326
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• 2016

This study was conducted to identify characteristics observed by staff during infertility treatment, and to analyze the relationship between the result of the treatment according to the ART infertility characteristics. In cooperation with an Obstetrics and Gynecology Hospital in Ulsan, data were collected from 344 people receiving infertility treatment from 2012-1013 and evaluated by cross-analysis, logistic regression analysis, and the ${\chi}^2$ test. Age 30 subjects (72.1%), no disease (70.9%), and no birth children (77.0%) were most common among patients. Causes of infertility factor is the higher the age, followed by uterine factors, ovarian factors were the lower the age.Were assisted reproduction are IUI (51.5%), IVF (23.0%), IUI + IVF (25.6%), assisted reproduction were age (p<.013) infertility period (p<.014), abortion Experience (p<.008) it was not statistically significant. ART pregnancies result was 34.9%, IUI was 49.2%, IVF was 50.8%. The average number of successful IVF treatment was 1.64, while it was 1.36 for IVF. IVF is 0.28 times lower than the IUI. Thus, low in order to increase the success rate of pregnancy according to the assisted reproduction age, nanim period is short, and if you do not have birth children choose artificial fertilization, and high age, IVF If there are nanim period is longer and birth child treatment and you must choose. This study analyzed all subjects who underwent fertility treatment to have research significance. However, it is difficult to generalize, locally called Sun City limits. If this one based on regional and national follow-up study of infertility therapist made it will help to prepare the way of effective treatment for infertility causes.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.34-40
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• 1999

Reed-Solomon(RS) codes have been employed to correct burst errors in applications such as CD-ROM, HDTV, ATM and digital VCRs. For the decoding RS codes, the Berlekamp-Massey algorithm, Euclidean algorithm and modified Euclidean algorithm(MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The advantages of the proposed scheme are twofold. First, The proposed architecture uses about 25% less clock cycles required in the MEA operation than[1]. Second, the number of recursive MEA cells can be reduced, when the number of clock cycles spent in the MEA operation is larger than code word length n. thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circurity for (128,124) RS code have been described and the MEA operation is verified through VHDL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.22-28
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• 2008

This paper designed a efficient 8-bit CMOS analog-to-digital converter(ADC) for an SOC(System On Chip) application. The architecture consists of two modified 4-bit full-flash ADCs, it has been designed using a more efficient architecture. This is to predict roughly the range in which input signal residers and can be placed in the proximity of input signal based on initial prediction. The prediction of input signal is made available by introducing a voltage estimator. For 4-bit resolution, the modified full-flash ADC need only 6 comparators. So a 8-bit ADC require only 12 comparators and 32 resistors. The speed of this ADC is almost similar to conventional full-flash ADC, but the die area consumption is much less due to reduce numbers of comparators and registors. This architecture uses even fewer comparator than half-flash ADC. The circuits which are implemented in this paper is simulated with LT SPICE tool of computer.