Journal of the Institute of Convergence Signal Processing (융합신호처리학회논문지)

The Korea Institute of Convergence Signal Processing (한국융합신호처리학회)
권호 표지

Design of a nonlinear ADC encoder to reduce the conversion errors in DBNS

DBNS 변환오차를 고려한 비선형 ADC 엔코더 설계

  • Received : 2013.09.05
  • Accepted : 2013.10.31
  • Published : 2013.10.30
Download PDF
⟨ Previous Next ⟩

Abstract

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

아날로그 신호를 입력받아서 실시간으로 처리하기 위해서는 빠른 곱셈 연산회로와 고속 ADC(A/D converter) 회로가 필요하며 이를 위하여 Double-base Number System(DBNS)이 효과적인 것으로 알려져 있다. DBNS는 2와 3을 밑수로 이용하는 시스템으로서 이진 곱셈기와 비교할 때 곱셈 처리가 매우 빠르며, 칩 면적을 감소시킬 수 있으며, 저소비전력의 장점을 갖고 있다. 그러나 DBNS의 고유특성 때문에 변환오차가 발생하며, 디지털 필터의 구조로 인하여 오차가 연산결과에 누적되어 기존에 사용하던 2진수 방식에 비하여 차단 주파수의 S/N 특성이 저하되는 단점이 있다. 본 논문에서는 필터 계수에 대한 오차를 분석하여 ADC의 엔코더를 비선형으로 설계함으로써 DBNS의 누적오차를 상쇄시키는 방법을 제안하였다. 제안된 시스템은 엔코더 회로만이 수정되었으므로 DBNS의 장점은 그대로 유지된다. 제안한 ADC 엔코더가 비선형임에도 불구하고 -70dB의 차단 주파수 특성을 갖도록 설계한 FIR 필터와 비교하면, 기존의 DBNS 엔코더의 결과는 -35dB를 얻을 수 있었지만, 본 연구에서 제안된 비선형 DBNS 엔코더는 -45dB의 S/N로 -10dB의 향상을 이룰 수 있었다.

Keywords

References

  1. Kacem R., Khouja N., Grati. K., Ghazel A., "Low Power Implementation of Digital Filters using DBNS Representation and Sub-expression Sharing", The 2nd International Conference on Signals, Circuits and Systems ,pp. 1-6, November 2008.
  2. Kriangyut Wangjitman and Athasit Surarerks, "Addition Transducer for Double Base Number System", ISCIT'06, pp. 994-999, September 2006.
  3. M. Pankaala, A. Paasio, and M. Laiho, "Implementation alternatives of a DBNS adder", 9th International Workshop on Cellular Neural Networks and Their Applications, pp. 138-141,May 2005,
  4. Amitabha, Kolkata, Pavel Sinha, Kenneth Alan Newton, Krishana Mulherjee, "Triple-Base Number Digital Signal and Numerical Processing System", US Patent, January 24, 2008.
  5. R. Muscedere, V. Dimitrov, G. A. Jullien, W. C. Miller, "Efficient Techniques for Binary-to-Multi digit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables", IEEE Trans. on Computers, vol.54, pp. 257-271,March 2005. https://doi.org/10.1109/TC.2005.48
  6. Vassil S. Dimitrov and Graham A. Jullien, "A New Number Representation with applications", IEEE Circuits and Systems Magazine, 2003.
  7. Vassil S. Dimitrov and Graham A. Jullien, and W. C. Miller, "Theory and Applications of the Double-Base Number System", IEEE Transactions on Computers, vol.48, pp. 1098 - 1106, 1999. https://doi.org/10.1109/12.805158
  8. V. Berthe, Laurent Imbert, and Graham A. Jullien, "More on Converting Numbers to the Double-Base Number System", Research Report LIRMM-0403 1, Montpellier France, October 2004.
  9. Y. Ibrahim, W. C. Miller, Graham A. Jullien, and Vassil S. Dimitrov, "DBNS Addition using Cellular Neural Networks", IEEE International Symposium on Circuits and Systems, vol. 4, pp. 3914-3917,May 2005.
  10. G. Gilbert and J. M. P. Langlois, "Multipath Greedy Algorithm for Canonical Representation of Numbers in the Double Base Number System", IEEE-NEWCAS Conference, pp. 39-42,June 2005.
  11. Nguyen Minh Son, et al, "Algorithm and Design of Double-Base Log Encoder for a Flash A/D Converter",신호처리.시스템학회논문지,vol 10, no. 4, pp. 289-293, October 2009.
  12. Nguyen Minh Son, et al, "New Multiplier for a Double-Base Number System linked to a Flash ADC", ETRI journal vol. 34, no. 2,pp. 256-259,April 2012. https://doi.org/10.4218/etrij.12.0211.0198
  13. H.-J. Kang and I.-C. Park, "FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders", IEEE Trans. Circuits Syst., vol 48, pp 770-778, Aug 2001. https://doi.org/10.1109/82.959867
  14. Bhaskar D. Rao, "Floating-point Arithmetic and Digital Filter", IEEE Trans. on Signal Processing, vol. 40, pp. 85-95,1992,
  15. Nguyen Minh Son, Jong-soo Kim, Jae-ha Choi, "A New Multiplication Architecture for DSP Applications", 신호처리.시스템학회논문지, vol12 no.2, pp.139-144, 2011.