1 |
M. Abramovici, C. Stroud, S. Wijesuriya, C. Hamilton, and V. Verma, 'Using Roving STARs for On-Line and Diagnosis of FPGAs in Fault-Tolerant Applications,' Proc. lTC, pp. 973-982, Oct. 1999
|
2 |
Xilinx Inc., http://www.xilinx.com
|
3 |
J. Cong and Y. -Yo Hwang, 'Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation,' Proc. ACM 6th Int'l Symposium on FPGA, pp. 27-34, Feb. 1998
|
4 |
M. Helliwell, and M. Perkowski, 'A Fast Algorithm to Minimize Multi-Output Mixed-Polarity Generalized Reed-Muller Forms,' Proc. ACM/IEEE Design Automation Conf., pp. 427-432, 1988
|
5 |
F. Hanchek and S. Dutt, 'Methodologies for Tolerating Logic and Interconnect Faults in FPGAs,' IEEE Trans. on Computers, Vol. 47, No. 1, pp. 15-33, Jan. 1998
DOI
ScienceOn
|
6 |
J. C. Lo, M. Kitakami and E. Fujiwara, 'Reliable Logic Citcuits using Byte Error Control Codes,' Proc. Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 286-294, October 1996
|
7 |
W. K. Huang, F. J. Meyer, X. Chen, and F. Lombardi, 'Testing Configurable LUT-Based FPGAs,' IEEE Trans. on VLSI Systems, Vol. 47, No.6, pp. 276-283, June 1998
|
8 |
S. B. Ko, T. Xia and J. C. Lo, 'Efficient Error Prediction in FPGA,' IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI systems, pp. 176-181, Oct. 2001
|
9 |
N. A. Touba, and E. J. McCluskey, 'Logic Synthesis of Multilevel Citcuits with Concurrent Error Detection,' IEEE Transactions on Computer-Aided Design, Vol.16, No.7, pp. 783-789, Jul. 1997
DOI
ScienceOn
|
10 |
J. Cong and Y. Ding, 'Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays,' ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 2, pp. 145-204, April 1996
DOI
|
11 |
T. Sasao and P. Besslich, 'On the complexity of MOD-2 Sum PLAs,' IEEE Transactions on Computers, Vol. 32, No.2, pp. 262-266, Feb. 1990
|
12 |
S. B. Ko and J. C. Lo, 'Efficient Decomposition Techniques for FPGAs,' Lecture Notes in Computer Science (IEEE International Conference on High Performance Computing), Vol. 552, pp. 630-639, December 2002, Springer-Verlag
|
13 |
S. Even, I. Kohavi and A. Paz, 'On minimal modulo-2 sums of products for switching functions,' IEEE Transactions on Electronic Computers, EC-16:671-674, Oct. 1967
DOI
ScienceOn
|
14 |
R. Cuddapah and M. Corba, Reconfigurable Logic for Fault Tolerance, Springer-Verlag, 1995
|
15 |
C. Bolchini, F. Salice and D. Sciuto, 'A Novel methodology for Designing TSC Networks based on the Parity Bit Code,' Proc. European Design & Test Conf., pp. 440-444, March 1997
|
16 |
Xinlinx Inc., Xilinx Data Book: XC4000E and XC4000X Series, May 1999
|
17 |
T. Sasao, 'Logic Synthesis and Optimization,' Kluwer Academic Publishers 1998
|