• Electronics and Telecommunications Trends
• /
• v.13 no.1 s.49
• /
• pp.41-51
• /
• 1998

전역 클럭을 사용하는 동기 회로 설계 기술은 설계의 단순화 및 자동화가 용이하기 때문에 현재 많이 사용하는 설계 기술이다. 그러나 다양한 기능과 고성능을 필요로 하는 대규모 시스템이나 회로 설계에서는 전역 클럭 사용으로 인한 신호 지연, 전력 소모 등이 문제로 부각되면서 비동기 회로 설계 기술이 각광을 받고 있다. 비동기 회로 설계 기술은 1940년대에 개발된 기술이지만 설계 자체가 어렵고 면적 증가 등의 단점으로 제한된 분야에서 이용되었다. 현재 이러한 단점을 극복하기 위한 연구가 회로 설계, 검증, 동기/비동기 인터페이스, 그리고 저전력 회로 등의 분야에서 많이 진행되고 있다.

• Proceedings of the KAIS Fall Conference
• /
• 2009.05a
• /
• pp.746-749
• /
• 2009

유비쿼터스 센서 네트워크에서 사용되는 센서노드는 동종의 센서 노드와 많은 수의 이기종 센서 노드들을 포함하게 된다. 이기종 센서노드들간의 시간동기화로 인한 배터리 전력소모를 최소화하기 위해서 본 논문에서는 싱크노드 아래에 있는 싱크노드와 클럭소스가 같은 동종 센서노드를 시간동기 마스터로 설정하고, 싱크노드와 다른 클럭소스를 가지는 다수의 이기종 센서노드를 마스터 아래에 속하는 시간동기 슬레이브로 설정하여 시간동기 마스터가 동작을 개시할 때에만 시간동기 슬레이브 노드들이 동작하도록 동기화하는 이기종 센서노드들의 시간동기화 기법을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.6B
• /
• pp.840-847
• /
• 2001

본 논문에서는 클럭 동기 회로에 사용되는 다차 함수 형태의 결합 필터를 선형 근사화 하는 알고리즘을 제안하고 이를 하드웨어로 구현한다. 정합 필터와 보간필터에 의한 클럭 동기회로는 수신기를 전 디지털 회로를 구현하기 위해 선호되지만 계산량이 증가하는 단점이 있다. 본 논문에서는 정합 필터의 임펄스 응답을 갖는 결합 보간 필터를 구현하고, base 함수의 적용을 선형 근사화 하여 필터의 계산량을 감소시켰다. 본 논문에서는 선형 근사화된 결합 보간 필터의 동작을 Matlab을 통한 시뮬레이션과 ALTERA Chip으로 테스트하였다.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.1
• /
• pp.69-74
• /
• 2003

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.4 s.119
• /
• pp.423-429
• /
• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.57-63
• /
• 2009

In this Paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuit is composed of CDR(Clock and Data Recovery) block and PLL(Phase Locked Loop) block. Lock dynamics is accomplished on the first data transition and data are sampled in the optimal point. The CDR circuit is realized in 0.35um CMOS process technology. With input pseudo-random bit sequences(PRBS) of $2^7-1$, the simulations show 17ps peak-to-peak retimed data jitter characteristics. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.6
• /
• pp.408-420
• /
• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.28-35
• /
• 2015

In this paper, we propose to identify redundant power states of high-level power model based on clock gating enable signals(CGENs) using dependencies of Boolean functions and structural dependencies of clock gating cells. Three functional dependencies between two CGENs, namely equvalence, inversion, and inclusion, are used. Functions of CGENs in a circuit are represented by binary decision diagrams (BDDs) and the functional relations are used to reduce the number of power states. The structural dependency appears when a clock gating cell drives another clock gating cells in a circuit. Automatic dependency checking algorithm has been proposed. The experimental results show the average number of power state is reduced by 59%.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.289-292
• /
• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39B no.5
• /
• pp.296-303
• /
• 2014

Reference Broadcast Synchronization (RBS) is one of the most prominent synchronization protocols in wireless sensor nework. Given that the broadcasting medium is available, RBS can give very high accuracy of synchronization. However, RBS uses instantaneous synchronization and results in time discontinuity, which might cause serious faults in the distributed system. Also, RBS lacks packet loss tolerance, which brings about degraded performance in severe conditions of wireless channel. In this paper, the problem of time discontinuity in RBS is pointed out and the effect of packet loss on the performance of RBS is examined. Then, a continuous synchronization and a packet loss tolerance mechanism for RBS are proposed, and the result is verified through simulations.