1 |
C.M. Lee, C.K. Chen, and R.S. Tsay. "A Basic-block Power Annotation Approach for Fast and Accurate Embedded Software Power Estimation," the International Conference on VLSI, pp. 118-123, Oct. 2013.
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2 |
G. Vijin, Oklobdzija, "The Computer Engineering Handbook," CRC Press,Dec. 2001
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3 |
H. Choi, "Reduction of the Number of Power States for High-level Power Models based on Clock Gating Signals," Kwangwoon university, Feb. 2015.
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4 |
N.F. Ghohroud. Z. Navabi, "Back-annoation of Gate-level Power Properties into System Level Descriptions" ICCC New Circuits and Systems Conference 12th, pp.237-240, Jun. 2014.
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5 |
I. Lee, H. Kim, S. Yoo, E. Y. Chung, K. M. Choi, J. K. Kong and S. K.. Eo. "Powervip: Soc power estimation framework at transaction level" In Proc. of South Pacific Design Automation Conference, pp.551-558, 2006.
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6 |
N. Bansal, K. Lahiri, A. Raghunathan, "Automatic Power Modeling of Infratructure IP for SystemonChip Power Analysis," 20th International Conference on VLSI Design, pp.513-520, 2007.
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7 |
J. Kim, J. Yi, "Case study on the High-Level Power Modeling Based on Clock Gating," 2013 IEIE summer Conference, pp. 1945-1948, Vol. 2013, No. 7, Jul. 2013.
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8 |
S. Wimer, I. Koren, I. Cederbaum "Design Flow for Flip-Flop Grouping in Data Driven Clock Gating" IEEE Transactions on VLSI Systems, Vol. 22, pp.771-778, May. 2013.
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9 |
R. Fraer, G. Kamhi, and M. K. Mhameed. "A new paradigm for synthesis and propagation of clock gating conditions" In Proc. of Design Automation Conference, pages 658-663, Jun. 2008.
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10 |
S.B. Aker,. "Binary decision diagrams," IEEE Transactions on Computers, Vol. C-27, no.6, pp. 509-516, Jun. 1978.
DOI
ScienceOn
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11 |
P.K. Sharma, N.K. Singh, "Improved BDD Compression by Combination of Variable Ordering Techniques" the International Conference on Communications and Signal Processing, pp.3-5, Apr. 2014.
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12 |
E. Albert, E. Ruehli, A.L. Sangiovannivincentelli, G. Rabbat, "Time Analysis of Large-Scale Circuits Containing One-Way Macromodels," IEEE Transactions on Circuits and Systems, Vol. 29, pp. 185-190, Mar. 1982.
DOI
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13 |
M.T. Kuo, T. Wang, "BDD-based Logic Partitioning for Sequential Circuits" Design Automation Conference, pp.607-612, Jan. 1997.
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14 |
Design Complier (http://www.synopsys.com)
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15 |
Colorado university decision diagram (CUDD) package (http://www.cs.uleth.ca/-rice/cudd.html)
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16 |
Floating Point Unit (opencore.ore/project,fpu)
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17 |
UART to Bus (opencore.ore/project,uart)
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18 |
H.264/AVC BaselineDecoder (opencore.ore/project,nova)
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