Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

A Wide - Range Dual-Loop DLL with Programmable Skew - Calibration Circuitry for Post Package

패키지후 프로그램을 이용 스큐 수정이 가능한 광범위한 잠금 범위를 가지고 있는 이중 연산 DLL 회로

  • Choi, Sung-Il (Division of Information Engineering and Telecommunications) ;
  • Moon, Gyu (Division of Information Engineering and Telecommunications) ;
  • Wee, Jae-Kyung (Division of Information Engineering and Telecommunications)
  • 최성일 (한림대학교 정보통신공학부) ;
  • 문규 (한림대학교 정보통신공학부) ;
  • 위재경 (한림대학교 정보통신공학부)
  • Published : 2003.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

이 논문에서는 1) 넓은 잠금 범위를 위한 이중 루프 동작과 2) 차세대 패키지 스큐 개선에 대한 전압 발생기와 안티퓨즈 회로를 사용한 프로그래머블 레프리카 딜레이, 두 가지 이점을 갖는 Delay Lock Loop(DLL)을 기술하였다. 이중 루프 동작은 차동 내부 루프 중 하나를 선택하기 위해 외부 클럭과 내부 클럭 사이의 초기 시간차에 대한 정보를 사용한다. 이를 이용하여 더 낮은 주파수로 DLL의 잠금 범위를 증가시킨다. 덧붙여서, 전압발생기와 안티퓨즈 회로를 사용한 프로그래머블 레프리카 딜레이의 결합은 패키지 공정 후에 온-오프 칩 변화로부터 발생하는 외부 클럭과 내부 클럭 사이에 스큐 제거를 해준다. 제안된 DLL은 0.16um 공정으로 제조되었고, 2.3v의 전원 공급과 42㎒ - 400㎒의 넓은 범위에서 동작한다. 측정된 결과는 43psec p-p 지터와 400㎒에서 52㎽를 소비하는 4.71psec 실효치(rms)지터를 보여준다.

Keywords

References

  1. A. Hatakeyama, et al., 'A 256-Mb SDRAM using a register-controlled digital DLL,' IEEE J. Solid-State Circuits, vol.32, pp. 1728-1734, Nov. 1997 https://doi.org/10.1109/4.641693
  2. Y. Okajima, et al., 'Digital delay locked loop and design technique for high-speed synchronous interface,' IEICE Trans. Electron., vol. E79-C, June 1996
  3. T. H. Lee, et al., 'A 2.5 V CMOS delay-locked loop and for an 18 Mbit, 500 Megabyte/s DRAM,' IEEE J. Solid-State Circuits, vol.29, pp. 1491-1496, Dec. 1994 https://doi.org/10.1109/4.340422
  4. S. Tanoi, et al., 'A 250-622MHz deskew and jitter-suppressed clock buffer using two-loop architecture,' IEEE J. Solid-State Circuits, vol. 31, pp. 487-493, Apr. 1996 https://doi.org/10.1109/4.499724
  5. S. Sidiropulos, et al., 'A semi-digital dual delay-locked loop,' IEEE J. Solid-State Circuits, vol.32, pp. 1683-1692, Nov. 1997 https://doi.org/10.1109/4.641688
  6. Y. Okuda, et al., 'A 66-400MHz, Adaptive-Lock-Mode DLL Circuit with Duty-Cycle Error Correction', Symp. VLSI Circuits Dig. Tech Papers, pp. 37-38, June 2001 https://doi.org/10.1109/VLSIC.2001.934188
  7. C. H. Park, et al., 'A low-noise, 900-MHz VCO in 0.6-${mu}m$ CMOS,' IEEE J. Solid-State Circuits, vol.34, pp. 586-591, May. 1999 https://doi.org/10.1109/4.760367
  8. T. Yoshimura, et al., 'A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories,' Symp. VLSI Circuits Dig. Tech. Papers, pp. 66-67, June 1998 https://doi.org/10.1109/VLSIC.1998.688006
  9. J. G. Maneatis, 'Low-jitter and process-independent DLL and PLL based on self-biased techniques,' IEEE J. Solid-State Circuits, vol.31, pp. 1728-1732, Nov. 1998 https://doi.org/10.1109/JSSC.1996.542317
  10. Ian A. Young, et al., 'A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors.' IEEE. J. Solid-State Circuits, vol.27, pp. 1599-1607, Nov. 1992 https://doi.org/10.1109/4.165341
  11. F. Herzel, et al., 'A Study of Oscillator jitter Due to Supply and Substrate Noise' IEEE TRAN. Circuit and System II, vol.46, pp. 56-62, Jan. 1999 https://doi.org/10.1109/82.749085
  12. T. Hamamoto, et al., 'A Skew and jitter Suppress DLL Architecture for high frequency DDR SDRAMs' Symp. VLSI Circuits Dig. Tech. Papers, pp. 76-77, June 2000
  13. S. Kuge, et al., 'A 0.18um 256Mb DDR-SDRAM with Low-Cost Post-Mold-Tuning Method for DLL Replica' ISSCC Dig. Tech. Papers, pp. 402-403, Feb. 2000 https://doi.org/10.1109/ISSCC.2000.839834
  14. K. S. Min, et al., 'A Post-Package Bit-Repair Scheme Using Static Latches with Bipolar-Voltage Programmable Antifuse Circuit for High-Density DRAMs' Symp. VLSI Circuits Dig. Tech. Papers, pp. 67-68 https://doi.org/10.1109/VLSIC.2001.934197
  15. Moon G. et al, 'An enhancement-mode mos-voltage-controlled linear resistor with large dynamic range' IEEE Transactions on circuits and systems, vol. 37, no. 10, pp. 1284-1288, october 1990 https://doi.org/10.1109/31.103222