Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Reduction of the Number of Power States for High-level Power Models based on Clock Gating Enable Signals

클럭 게이팅 구동신호 기반 상위수준 전력모델의 전력 상태 수 감소

  • Choi, Hosuk (Dept. of Computer Engineering, Kwangwoon University) ;
  • Yi, Joonhwan (Dept. of Computer Engineering, Kwangwoon University)
  • 최호석 (광운대학교 컴퓨터공학과) ;
  • 이준환 (광운대학교 컴퓨터공학과)
  • Received : 2015.02.02
  • Accepted : 2015.09.07
  • Published : 2015.09.25
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Abstract

In this paper, we propose to identify redundant power states of high-level power model based on clock gating enable signals(CGENs) using dependencies of Boolean functions and structural dependencies of clock gating cells. Three functional dependencies between two CGENs, namely equvalence, inversion, and inclusion, are used. Functions of CGENs in a circuit are represented by binary decision diagrams (BDDs) and the functional relations are used to reduce the number of power states. The structural dependency appears when a clock gating cell drives another clock gating cells in a circuit. Automatic dependency checking algorithm has been proposed. The experimental results show the average number of power state is reduced by 59%.

본 논문은 클럭 게이팅 구동신호를 이용한 전력 모델링 방법에서 회로에서 나타나지 않는 잉여 전력 상태를 확인함으로써 전력 상태 수를 줄이는 방법을 제안한다. 회로에 나타나지 않는 전력 상태를 확인하기 위해 함수적 종속성과 구조적 종속성을 확인한다. 본 논문에서는 2개의 클럭 게이팅 구동신호 간에 나타나는 함수적 종속성 중 동치 관계, 역관계, 포함 관계만을 다룬다. 구조적 종속성은 클럭 게이팅 셀의 위치적 특성에 의한 종속성을 의미한다. 두 종속성으로 발견한 관계를 이용해 전력상태의 수를 줄였으며, 감소 후 남은 전력 상태수를 세기위해 이진결정다이어그램을 사용하였다. 함수적 종속성과 구조적 종속성을 이용해 전력 상태 수를 알고리즘 적용 전 대비 평균 59%까지 감소시켰다.

Keywords

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