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A Wide - Range Dual-Loop DLL with Programmable Skew - Calibration Circuitry for Post Package  

Choi, Sung-Il (Division of Information Engineering and Telecommunications)
Moon, Gyu (Division of Information Engineering and Telecommunications)
Wee, Jae-Kyung (Division of Information Engineering and Telecommunications)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.40, no.6, 2003 , pp. 408-420 More about this Journal
Abstract
This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.
Keywords
DLL; Skew-calibration circuit; Antifuse circuitry;
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1 A. Hatakeyama, et al., 'A 256-Mb SDRAM using a register-controlled digital DLL,' IEEE J. Solid-State Circuits, vol.32, pp. 1728-1734, Nov. 1997   DOI   ScienceOn
2 T. H. Lee, et al., 'A 2.5 V CMOS delay-locked loop and for an 18 Mbit, 500 Megabyte/s DRAM,' IEEE J. Solid-State Circuits, vol.29, pp. 1491-1496, Dec. 1994   DOI   ScienceOn
3 Y. Okajima, et al., 'Digital delay locked loop and design technique for high-speed synchronous interface,' IEICE Trans. Electron., vol. E79-C, June 1996
4 S. Sidiropulos, et al., 'A semi-digital dual delay-locked loop,' IEEE J. Solid-State Circuits, vol.32, pp. 1683-1692, Nov. 1997   DOI   ScienceOn
5 J. G. Maneatis, 'Low-jitter and process-independent DLL and PLL based on self-biased techniques,' IEEE J. Solid-State Circuits, vol.31, pp. 1728-1732, Nov. 1998   DOI   ScienceOn
6 C. H. Park, et al., 'A low-noise, 900-MHz VCO in 0.6-${mu}m$ CMOS,' IEEE J. Solid-State Circuits, vol.34, pp. 586-591, May. 1999   DOI   ScienceOn
7 S. Tanoi, et al., 'A 250-622MHz deskew and jitter-suppressed clock buffer using two-loop architecture,' IEEE J. Solid-State Circuits, vol. 31, pp. 487-493, Apr. 1996   DOI   ScienceOn
8 Y. Okuda, et al., 'A 66-400MHz, Adaptive-Lock-Mode DLL Circuit with Duty-Cycle Error Correction', Symp. VLSI Circuits Dig. Tech Papers, pp. 37-38, June 2001   DOI
9 T. Yoshimura, et al., 'A Delay-Locked Loop and 90-degree Phase Shifter for 800Mbps Double Data Rate Memories,' Symp. VLSI Circuits Dig. Tech. Papers, pp. 66-67, June 1998   DOI
10 F. Herzel, et al., 'A Study of Oscillator jitter Due to Supply and Substrate Noise' IEEE TRAN. Circuit and System II, vol.46, pp. 56-62, Jan. 1999   DOI   ScienceOn
11 Moon G. et al, 'An enhancement-mode mos-voltage-controlled linear resistor with large dynamic range' IEEE Transactions on circuits and systems, vol. 37, no. 10, pp. 1284-1288, october 1990   DOI   ScienceOn
12 Ian A. Young, et al., 'A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors.' IEEE. J. Solid-State Circuits, vol.27, pp. 1599-1607, Nov. 1992   DOI   ScienceOn
13 T. Hamamoto, et al., 'A Skew and jitter Suppress DLL Architecture for high frequency DDR SDRAMs' Symp. VLSI Circuits Dig. Tech. Papers, pp. 76-77, June 2000
14 S. Kuge, et al., 'A 0.18um 256Mb DDR-SDRAM with Low-Cost Post-Mold-Tuning Method for DLL Replica' ISSCC Dig. Tech. Papers, pp. 402-403, Feb. 2000   DOI
15 K. S. Min, et al., 'A Post-Package Bit-Repair Scheme Using Static Latches with Bipolar-Voltage Programmable Antifuse Circuit for High-Density DRAMs' Symp. VLSI Circuits Dig. Tech. Papers, pp. 67-68   DOI