• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.26 no.5
• /
• pp.682-687
• /
• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.10a
• /
• pp.614-615
• /
• 2016

I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.529-530
• /
• 2017

Electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET) was investigated. Depending on the thickness of Inter Layer Dielectirc (ILD) between top and bottom JLFETs, $N_{gate}-N_{gate}$ capacitance and transconductance $g_m$ are changed by the gate voltage of bottom JLFET. Therefore, when using a stacked structure with the ILD below tens nm, AC electrical coupling between two transistors in M3D-INV should be considered.

• Electrical & Electronic Materials
• /
• v.3 no.4
• /
• pp.271-278
• /
• 1990

본 논문에서는 내부전극 Pt를 갖는 적층형 압전액튜에이터의 제조와 적층수에 따른 압전액튜에이터 압전특성에 대해 조사 연구하였다. 먼저, Dr.blade방법을 사용하여 두께 ~220.mu.m의 PZT green sheet를 제작하였다. green sheet의 밀도는 결합제 양과 외부압력에 대해 크게 의존하였으며 소결체의 밀도는 green sheet의 밀도가 커질수록 더 높게 나타났다. 다음에는 적층수에 따른 압전정수의 변화에 대한 것으로써 압전정수(d$_{33}$)는 PZT세라믹스의 적층수가 증가할수록 매우 크게 증가되었으며 압전정수를 도입하여 계산된 변형량(.DELTA.l/l)은 10층 시편에 대해 2*$10^{6}$V/m의 전계에서 3*$10^{-3}$값을 얻었다. 이와같은 결과로써 적층형 압전액튜에이터는 저전압에서도 큰 변위를 나타내며 따라서 제어장치의 미세작동에 충분히 이용 될 수가 있다.다.

• Journal of the Korea institute for structural maintenance and inspection
• /
• v.28 no.1
• /
• pp.90-97
• /
• 2024

In this study, we employed Highly Ductile Cement Composite (HDCC) to evaluate the flexural performance of a RC slab that simulates the laminating structure of a seashell. To evaluate flexural performance, we produced conventional RC slab specimens, HDCC slab specimens, and HDCC-M slab specimens which biomimics a seashell's layered structure by inserting PE mesh inside the slab made of HDCC. A series of 4-point bending tests were conducted. Experimental results shows the flexural strength of the HDCC-M slab specimen was 1.7 times and 1.2 times higher than that of the RC and HDCC slab specimens, respectively. Furthermore, the ductility was evaluated using the ratio of yield deflection to maximum deflection, and it was confirmed that the HDCC slab test specimen exhibited the best ductility. This is most likely due to the fact that the inserted PE mesh separates the layers and increases ductility, while the HDCC passing through the mesh prevents the loss of load carrying capacity due to layer separation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.10 no.1
• /
• pp.70-77
• /
• 1999

A miniaturized voltage controlled oscillator using multi-layer ceramic technology at PCS frequency band is designed and fabricated. To improve the phase noise characteristics and to reduce the size, the strip line which is embedded in a high performance multi-layer ceramic substrate is used as an inductor of VCO. And the fabricated VCO is very small size ($6mm\times6mm\times2mm$). At the bias condition of 3.3 V and 9mA, the output power and phase noise in the operating frequency range of 1,720~1,780 MHz are -3.7 dBm and -95 dBc/Hz at 10 KHz offset from the carrier, respectively. The phase noise and size are better than the conventional VCO using glass epoxy substrate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.10a
• /
• pp.118-120
• /
• 2022

This paper investigated the change of threshold voltage according to the influence of work-function variation (WFV) of metal gate in the device structure of monolithic 3-dimension inverter (M3DINV). In addition, in order to investigate the change in threshold voltage according to the electrical coupling of the NMOS stacked on the PMOS, the gate voltages of PMOS were applied as 0 and 1 V and then the electrical coupling was investigated. The average change in threshold voltage was measured to be 0.1684 V, and they standard deviation was 0.00079 V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2022.05a
• /
• pp.481-482
• /
• 2022

In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.112-117
• /
• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.632-635
• /
• 2008

In this paper, a diplexer circuit to separate GSM/CDMA band is designed using a LTCC (Low Temperature Cofired Ceramic) multi-layer technology. In order to increase a integration capability of the diplexer, it is designed in 6-layer LTCC sunstrate with a elative dielectric constant of 7.2 using 3-dimensional (3-D) multi-layer inductors and capacitors. The size of the designed diplexer including CB-CPW pads is $3,450{\times}4,000{\times}600{\mu}m^3$. An insertion loss (IL) and return loss of GSM band are less than -0.23dB and -10dB, respectively. In the case of CDMA band, the IL of -0.53dB and RL of below -10dB are archieved.