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http://dx.doi.org/10.6109/jkiice.2022.26.5.682

Study of monolithic 3D integrated-circuit consisting of tunneling field-effect transistors  

Yu, Yun Seop (ICT&Robotics Eng. and IITC, Hankyong National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.26, no.5, 2022 , pp. 682-687 More about this Journal
Abstract
In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.
Keywords
Monolithic 3-dimensional integrated-circuits; tunnel field-effect transistor; layout design; voltage transfer characteristics;
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1 P. G. Emma and E. Kursun, "Is 3D chip technology the next growth engine for performance improvement?," IBM J. Res. Develop., vol. 52, no. 6, pp. 541-552, Nov. 2008.   DOI
2 W. Cheng, R. Liang, G. Xu, G. Yu, S. Zhang, H. Yin, C. Zhao, T. -L. Ren, and J. Xu, "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," IEEE Journal of the Electron Devices Society, vol. 8, pp. 336-340, Mar. 2020. DOI: 10.1109/JEDS. 2020.2981974.   DOI
3 Y. S. Yu and F. Najam, "Compact capacitance model of L-shape tunnel field-effect transistor for circuit simulation," Journal of information and communication convergence engineering, vol. 19, no. 4, pp. 263-268, Dec. 2021. DOI: 10.6109/jicce.2021.19.4.263.   DOI
4 International Roadmap for Devices and Systems (IRDSTM) 2021 Edition [Internet]. Available: https://irds.ieee.org/editions/2021/more-moore.
5 D. K. Nayak, S. Banna, S. K. Samal and S. K. Lim, "Power, performance, and cost comparisons of monolithic 3D ICs and TSV-based 3D ICs," in Proceeding of 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park; CA, pp. 1-2, 2015. DOI: 10.1109/S3S.2015.7333538.   DOI
6 J. H. Kim, S. Kim, and B. -G. Park, "Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si," IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 1656-1661, Apr. 2019. DOI: 10.1109/TED.2019.2899206.   DOI
7 P. S. Kanhaiya, Y. Stein, W. Lu, J. A. del Alamo, and M. M. Shulaker, "X3D: Heterogeneous Monolithic 3D Integration of "X" (Arbitrary) Nanowires: Silicon, III-V, and Carbon Nanotubes," IEEE Transactions on Nanotechnology, vol. 18, pp. 270-273, Mar. 2019. DOI: 10.1109/TNANO.2019. 2902114.   DOI
8 S. Strangio, F. Settino, P. Palestri, M. Lanuzza, F. Crupi, D. Esseni, L. Selmi, "Digital and analog TFET circuits: Design and benchmark," Solid-State Electronics, vol. 146, pp. 50-65, Aug. 2018. DOI:10.1016/j.sse.2018.05.003.   DOI
9 Silvaco Int. ATLAS ver. 5. 30. 0. R Manual; Silvaco Int.: Santa Clara, CA, USA, 2020.