• Title/Summary/Keyword: 이중 채널 통신

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Analysis of Subthreshold Swing for Channel Length of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET의 채널길이에 대한 문턱전압이하 스윙 분석)

  • Jung, Hakkee;Lee, Jongin;Cheong, Dongsoo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2014.10a
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    • pp.745-748
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    • 2014
  • 본 연구에서는 비대칭 이중게이트(double gate; DG) MOSFET의 채널길이에 대한 문턱전압이하 스윙의 변화에 대하여 분석하였다. 문턱전압이하 스윙은 트랜지스터의 디지털특성을 결정하는 중요한 요소로서 채널길이가 감소하면 특성이 저하되는 문제가 나타나고 있다. 이러한 문제를 해결하기 위하여 개발된 DGMOSFET의 문턱전압이하 스윙의 채널길이에 대한 변화를 채널두께, 산화막두께, 상하단 게이트 전압 및 도핑농도 등에 따라 조사하고자 한다. 특히 하단 게이트 구조를 상단과 달리 제작할 수 있는 비대칭 DGMOSFET에 대하여 문턱전압이하 스윙을 분석함으로써 하단 게이트 전압 및 하단 산화막 두께 등에 대하여 자세히 관찰하였다. 문턱전압이하 스윙의 해석학적 모델을 구하기 위하여 포아송방정식에서 해석학적 전위분포모델을 유도하였으며 도핑분포함수는 가우스분포함수를 사용하였다. 결과적으로 문턱전압이하 스윙은 상하단 게이트 전압 및 채널도핑농도 그리고 채널의 크기에 매우 민감하게 변화하고 있다는 것을 알 수 있었다.

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Partial CSI-Based Cooperative Power Allocation in Multi-Cell Dual-Hop MISO Relay Systems (다중-셀 이중-홉 MISO 릴레이 시스템에서 부분 채널 정보를 이용한 협력 전력 할당 기법)

  • Cho, Hee-Nam;Kim, Ah-Young;Lee, Jin-Woo;Lee, Young-Hwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.9C
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    • pp.887-895
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    • 2009
  • This paper proposes a cooperative power allocation with the use of partial channel information (e.g., the average signal-to-noise ratio (SNR) and transmit correlation) in multi-cell dual-hop multi-input single-output (MISO) relay systems. In a dual-hop MISO relay channel, it is desirable to allocate the transmit power between dual-hop links to maximize the end-to-end capacity. We consider the maximization of the end-to-end capacity of a dual-hop MISO relay channel under sum-power constraint. The proposed scheme adaptively allocates the transmit power considering the average channel gain of the target relay and the transmit correlation of the desired and inter-relay interference channel from adjacent relays. It is shown by means of upper-bound analysis that the end-to-end capacity can be maximized by making the angle difference of the principal eigenvectors of the desired and inter-relay interference channel orthogonal in highly-correlated channel environments. Finally, the performance of the proposed scheme is verified by computer simulation.

Performance Analysis of Dual-Layer Differential Precoding Technique Using 8-PSK Constellation (8-PSK 성운을 이용하는 이중계층 차분 선부호화 기법의 성능 분석)

  • Park, Noe-Yoon;Kim, Young-Ju
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.5
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    • pp.401-408
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    • 2013
  • Dual-layer differential codebook using 8-PSK (phase shift keying) constellation as its codeword elements, is proposed for Long term evolution (LTE) and/or LTE-Advanced systems. Due to the temporal correlation of the adjacent channel matrices, the consecutive precoding matrices are likely to be similar. This approach quantize only the differential information of the channel instead of the whole channel subspace, which virtually increase the codebook size to realize more accurate quantization of the channel. Especially, the proposed codebook has the same properties of LTE release-8 codebook that is, constant modulus, complexity reduction, and nested property. The mobile station can be designed by using less expensive non-linear amplifier utilizing constant modulus property. Computer simulations show that the capacity of the proposed dual-layer codebook performs almost 1.2dB better than those of any other non-differential codebooks with the same amount of feedback information.

Analysis of Threshold Voltage for Symmetric and Asymmetric Oxide Structure of Double Gate MOSFET (이중게이트 MOSFET의 대칭 및 비대칭 산화막 구조에 대한 문턱전압 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.12
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    • pp.2939-2945
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    • 2014
  • This paper has analyzed the change of threshold voltage for oxide structure of symmetric and asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET can be fabricated with different top and bottom gate oxide thickness, while the symmetric DGMOSFET has the same top and bottom gate oxide thickness. Therefore optimum threshold voltage is considered for top and bottom gate oxide thickness of asymmetric DGMOSFET, compared with the threshold voltage of symmetric DGMOSFET. To obtain the threshold voltage, the analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. We investigate for bottom gate voltage, channel length and thickness, and doping concentration how top and bottom gate oxide thickness influences on threshold voltage using this threshold voltage model. As a result, threshold voltage is greatly changed for oxide thickness, and we know the changing trend greatly differs with bottom gate voltage, channel length and thickness, and doping concentration.

Relation of Threshold Voltage and Scaling Theory for Double Gate MOSFET (DGMOSFET의 문턱전압과 스켈링 이론의 관계)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.5
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    • pp.982-988
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    • 2012
  • This paper has presented the relation of scaling theory and threshold voltage of double gate(DG) MOSFET. In the case of conventional MOSFET, current and switching frequency have been analyzed based on scaling theory. To observe the possibility of application of scaling theory for threshold voltage of DGMOSFET, the change of threshold voltage has been observed and analyzed according to scaling theory. The analytical potential distribution of Poisson equation has been used, and this model has been already verified. To solve Poisson equation, charge distribution such as Gaussian function has been used. As a result, it has been observed that threshold voltage is grealty changed according to scaling factor and change rate of threshold voltages is traced for scaling of doping concentration in channel. This paper has explained for the best modified scaling theory reflected the influence of two gates as using weighting factor when scaling theory has been applied for channel length and channel thickness.

Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 도핑분포함수에 따른 DIBL)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2643-2648
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    • 2015
  • This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

Outage Probability Analysis of Full Duplex Relay with Decode and Forward Protocol (복호 후 전달 방식을 사용하는 전이중 통신 릴레이 시스템에서의 오수신 확률 성능 분석)

  • Kwon, Tae-Hoon;Lim, Sung-Mook;Park, Sung-Soo;Hong, Dae-Sik
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.6A
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    • pp.568-576
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    • 2010
  • In this paper, we analyze the outage probability of full duplex relay (FDR) with decode-and-forward (DF) protocol is derived under fading channels. The fading channel for source-relay link is assumed to be Rician fading to consider the infrastructured fixed relay with line of sight (LOS) propagation, and the other fading channels are assumed to be Rayleigh fading. Based on this analytical result, we provide the criterion that FDR shows a lower outage probability than HDR to consider the interference problem and the resource efficiency improvement by full duplex (FD) operation. The accuracy of the analysis is confirmed throughout the simulation results.

Design and Implementation of a Dual-Channel ZigBee Router (이중 채널 ZigBee 라우터의 설계 및 구현)

  • Kim, Brian
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.2
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    • pp.416-421
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    • 2007
  • ZigBee is becoming a promising communication protocol for wireless sensor networks based on low-power consumption. In case of a ZigBee network requesting continuous transmission of sensed data, the required bandwidth can be overwhelm the maximum transmission rate of 150Kbps. However, the ZigBee router which delivers data from source node to destination node can transmit data at most in a half of maximum rate because the router can not send and receive the data simultaneously. In this paper, we propose and implement a dual-channel router which can send and receive data simultaneously. Also, we propose a centralized channel allocation algorithm to allocate different channels to each module. The experiment result by the proposed dual-channel router shows a maximum throughput of 150Kbps as large as twice of normal single-channel router.

Relation of Breakdown Voltage and Channel Doping Concentration of Sub-10 nm Double Gate MOSFET (10 nm 이하 DGMOSFET의 항복전압과 채널도핑농도의 관계)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.6
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    • pp.1069-1074
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    • 2017
  • Reduction of breakdown voltage is serious short channel effect (SCE) by shrink of channel length. The deviation of breakdown voltage for doping concentration is investigated with structural parameters of sub-10 nm double gate (DG) MOSFET in this paper. To analyze this, thermionic and tunneling current are derived from analytical potential distribution, and breakdown voltage is defined as drain voltage when the sum of two currents is $10{\mu}A$. As a result, breakdown voltage increases with increase of doping concentration. Breakdown voltage decreases by reduction of channel length. In order to solve this problem, it is found that silicon and oxide thicknesses should be kept very small. In particular, as contributions of tunneling current increases, breakdown voltage increases.

Dependence of Subthreshold Current for Channel Structure and Doping Distribution of Double Gate MOSFET (DGMOSFET의 채널구조 및 도핑분포에 따른 문턱전압이하 전류의존성)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.4
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    • pp.793-798
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    • 2012
  • In this paper, dependence of subthreshold current has been analyzed for doping distribution and channel structure of double gate(DG) MOSFET. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. Since DGMOSFETs have reduced short channel effects with improvement of current controllability by gate voltages, subthreshold characteristics have been enhanced. The control of current in subthreshold region is very important factor related with power consumption for ultra large scaled integration. The deviation of threshold voltage has been qualitatively analyzed using the changes of subthreshold current for gate voltages. Subthreshold current has been influenced by doping distribution and channel dimension. In this study, the influence of channel length and thickness on current has been analyzed according to intensity and distribution of doping.