• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.183-190
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• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.317-326
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• 2016

In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2277-2278
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• 2008

전력계통에서의 과전압은 계통의 상태 또는 외부상태인 대기의 방전의 결과로써 기원한다. 낙뢰에 의한 뇌서지는 여러 과전압 중에서 가장 큰 전압을 가진다. 절연요구사항에 대한 뇌 과전압의 크기를 특정화하고, 절연 섬락을 발생하는 위험한 뇌격전류를 발견하는 것은 전력계통의 설비 보호를 위한 중요한 요소이다. 본 논문에서는 과도해석 프로그램인 EMTP를 이용하여 송전선로 및 철탑을 모델링하고, 낙뢰에 인한 과전압이 발생하였을 때 송전선로 및 철탑에 어떻게 영향을 미치는지 모의하고 분석하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1877-1886
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• 2010

In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2069-2071
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• 2005

본 연구에서는 플라즈마 식각 공정 시 식자률, 선택비, wafer 손상등과 중요한 관련이 있는 이온 에너지 분포(IED)를 측정하기 위해서 챔버 내에 직접적으로 분석기를 설치하지 않고 챔버 외부에서 비 침투적(noninvasive)인 방법을 사용하여 측정하였다. 이 방범은 신호선 중 한 곳에 측정 점을 잡기 위한 연결 장치만 필요하며 그곳에서의 전안 신호와 전류 신호를 오실로스코프에서 측정한 후 미리 얻어진 챔버 구조 모델링 계수 등을 통해 실제 바이어스 전극에 걸리는 전압 및 전극에서 플라즈마로 흐르는 전류를 유추한다. 전압 및 전류측정값과 power balance와 particle balance를 적용하여 얻은 플라즈마 특성 상태 변수들을 사용하여 oscillating step sheath model을 기반으로 한 분석 프로그램을 통해 실시간 이온에너지 분포 결과를 얻었다. 실제 공정 시 바이어스 주파수 변화, 바이어스 파워 변화, 소스 파워변화 조건 등에 따른 이온 에너지 분포 측정 및 분석을 통해 비 침투적측정방법 적용의 가능성과 장점을 확인하였다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.6
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• pp.15-19
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• 2001

This paper presents an modelling and analysis of SSSC and UPFC in static analysis of power systems. SSSC is used to control active power flow in transmission lines by controlling the phase angle of the injected voltage source which is in rectangular to the line current. UPEC is used to control the magnitude and phase of the injected voltage sources which are connected both in series and in parallel with the transmission line to control power flow and bus voltage. To compare the effect of SSSC and UPFC in power system static analysis, the PSS/E simulation program is used. As the FACTS device model such as SSSC and UPFC is not provided in PSS/E yet, an equivalent load model is used. This procedure is implemented by IPLAN which is an external macro program of PSS/E. The simulation results show that UPFC is more effective to improve bus voltage than SSSC in power system static analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• Journal of IKEEE
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• v.24 no.1
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• pp.319-325
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• 2020

In this paper, a discontinuous-conduction mode (DCM) DC-DC buck converter is presented for mobile device applications. The buck converter consists of compensator for stable operations, pulse-width modulation (PWM) logic, and power switches. In order to achieve small hardware form-factor, the number of off-chip components should be kept to be minimum, which can be realized with simple and efficient frequency compensation and digital soft start-up circuits. Burst-mode operation is included for preventing the efficiency from degrading under very light load condition. The DCM DC-DC buck converter is fabricated with 0.18-um BCDMOS process. Programmable output with external resistors is typically set to be 1.8V for the input voltage between 2.8 and 5.0V. With a switching frequency of 1MHz, measured maximum efficiency is 92.6% for a load current of 100mA.

• Journal of IKEEE
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• v.13 no.3
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• pp.1-6
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• 2009

In this paper, the external matching circuits were designed in order to compensate the efficiency which decreases by human body effect in the internal antenna phone. Comparing the two types of matching circuit, we selected the structure to minimize the switch stress. RF MEMS switch using low voltage was compared with FET switch and measured the performance in the handset. Here, the detection circuit which can couple th reflection power from antenna was added in the handset and we set up the demonstration system that can compensate the loss of hand effect automatically. In this system, when hand effect occurred, the radiation power increased 2.5dB by operation the matching circuit.