• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.23-30
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• 2006

This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.149-156
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• 2013

This paper presents a hardware edge detector of image signal at pixel level of CMOS image sensor (CIS). The circuit detects edges of an image based on a bump circuit combining with the pixels. The APS converts light into electrical signals and the bump circuit compares the brightness between the target pixel and its neighbor pixels. Each column on CIS 64 by 64 pixels array shares a comparator. The comparator decides a peak level of the target pixel comparing with a reference voltage. The proposed edge detector is implemented using 0.18um CMOS technology. The circuit shows higher fill factor 34% and power dissipation by 0.9uW per pixel at 1.8V supply.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.2
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• pp.163-168
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• 2003

Several equipments for flame detection are employed in the power generations. But these flame detectors have some problems for the correct performance. So in this paper, we apply different techniques for the flame detection. Image processing techniques are broadly applied in industrial fields. In this paper, the image information is recorded by a camcoder and then these images are preprocessed for the input values of neural network model. We can test and evaluate the approach that uses image information for the flame detection of burners. If this technique is implemented in physical plant, the economical and effective operation could be achieved.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.325-328
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• 2008

본 논문에서는 비선형 모델의 설계를 위해 Type-2 퍼지 논리 집합을 이용하여 불확실성 문제를 다룬다. 퍼지 논리 시스템의 멤버쉽 함수와 규칙의 구조는 불확실성이 존재하는 언어적인 정보 또는 수치적 데이터를 바탕으로 설계된다. 기존의 Type-1 퍼지 논리 시스템은 외부의 노이즈와 같은 불확실성을 효율적으로 취급할 수 없다. 그러나 Type-2 퍼지 논리 시스템은 불확실한 정보까지 멤버쉽 함수로 표현함으로서 불확실성을 효과적으로 다룰 수 있다. 따라서 본 논문에서는 규칙의 전 ${\cdot}$ 후반부가 Type-2 퍼지 집합으로 구성된 Type-2 퍼지 논리 시스템을 설계하고 불확실성의 변화에 대한 비선형 모델의 성능을 비교한다. 여기서 규칙 전반부 멤버쉽 함수의 정점 선택은 C-means 클러스터링 알고리즘을 이용하고, 규칙 후반부 퍼지 집합의 정점 결정에는 입자 군집 최적화(PSO : Particle Swarm Optimization) 알고리즘을 사용한다. 마지막으로, 비선형 모델 평가에 대표적으로 이용되는 가스로 시계열 데이터를 제안된 모델에 적용하고, 입력 데이터에 인위적인 노이즈가 포함되었을 경우 Type-2 퍼지 논리 시스템이 기존의 Type-1 퍼지 논리 시스템보다 우수함을 보인다.

• Proceedings of the Korea Technology Innovation Society Conference
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• 2017.11a
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• pp.479-479
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• 2017

본 연구는 벤처기업의 매출액의 영향요인에 대하여 기업 내 자원을 범주화하여 그 영향력을 검증하고, 나아가 기업이 보유한 역량을 2개의 차원으로 구분하여 각 차원에 따른 집단 간 벤처기업성과 영향요인의 차이를 확인하고자 하였다. 즉, 기업이 보유하는 역량인 기술, 가격, 품질, 디자인, 조직관리, 마케팅 경쟁력에 대하여 요인분석을 통해 기술역량과 경영역량 차원을 도출하였고, 군집화 과정을 거쳐 각 역량 수준에 따른 네 개의 벤처기업 집단을 분류하였다. 네 개의 집단은 기술-경영 우위, 기술주도, 경영주도, 기술-경영 열위로 나뉘었다. 이후 성과 영향요인들을 자원기반이론의 관점에서 기업현황, 기업가자원, 인적자원, 재무자원, 기술자원, 외부자원의 여섯 개의 상위 범주로 구분하였고, 각 범주에 포함되는 세부 요인들이 매출액에 미치는 영향을 '벤처기업정밀실태조사'의 2개년 데이터를 활용하여 분석하였다. 분석 결과 첫 번째, 전체 벤처기업을 대상으로 분석한 결과 모형에 투입된 33개의 변수들 중 22개의 변수가 벤처기업 매출액에 유의한 영향을 미치는 것이 확인되었다. 두 번째, 기업 역량 차원 분류에 따른 기업 집단 간 영향요인 차이를 분석한 결과, 매출액 영향요인은 입력된 33개의 독립변수 중 최대 13개에서 최소 8개로, 기업 역량 차원에 따른 매출액 영향요인의 차이가 확인되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.77-85
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• 2008

This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

• Proceedings of the Korean Institute Of Construction Engineering and Management
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• autumn
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• pp.585-588
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• 2003

This study attempts to develop a skeleton model to link construction schedule and 3D object for drawings in 4D system. Generally, the construction schedule and 3D object can be linked in 4D system by imported files which are made in specific S/Ws such as CAD S/W and scheduling S/W. Those methods have a difficulties for operating 4D data because extra work needs to link 4D data for each activity. This study develops a 4D model which the 4D data can be self-generated within the system. The suggested model can reduce the initial input data for new project by integrating schedule and 3D object in 4D system.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.11a
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• pp.151-155
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• 2005

Though the nuclear fusion system has been fused into hydro-nuclear based on thermodynamics by tokamak system, there has been no success story. Because it's impossible to confine high temperatured plasma long Time actually. New nuclear-fusion-system using this nuclear-fusion-method will gather toroidal-magnetic-field by putting Core Block(C shaped torus iron) and toroidal-aluminium coil into toroidal magnetic-field-aluminium. That will arrange the nuclear-fusion-route on a gap fallen out by a part of cut torus-core and mkee the toroidal-an electric-current flow and electrolyze the fusioned-material (an electrolyte) into troidal-electrocity. That consists of troidal-magnetic-fild coil, toroidal-coial fusioned- material, series circuit. So toroidal-electocity will be changed into filament-electrocity and be introjected into fusioned-material. In a sapce on filament-electrocity, the magnetic inhaling-powr will enlarge to input-electrocity outside. This will exceed the Coulomb force and reache the nuclear-fusion. By this phenomenon there be quantity-loss. By this process I could confirmed that Einstein euation$(E=mC^2)$ releases into thermal energy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.