• Journal of the Korean institute of surface engineering
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• v.38 no.3
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• pp.89-94
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• 2005

We investigate the reaction stability of cobalt and nickel with side-wall materials of $SiO_2\;and\;Si_3N_4$. We deposited 15nm-Co and 15nm-Ni on $SiO_2(200nm)/p-type$ Si(100) and $Si_3N_4(70 nm)/p-type$ Si(100). The samples were annealed at the temperatures of $700\~1100^{\circ}C$ for 40 seconds with a rapid thermal annealer. The sheet resistance, shape, and composition of the residual materials were investigated with a 4-points probe, a field emission scanning electron microscopy, and an AES depth profiling, respectively. Samples of annealed above $1000^{\circ}C$ showed the agglomeration of residual metals with maze shape and revealed extremely high sheet resistance. The Auger depth profiling showed that the $SiO_2$ substrates had no residual metallic scums after $H_2SO_4$ cleaning while $Si_3N_4$ substrates showed some metallic residuals. Therefore, the $SiO_2$ spacer may be appropriate than $Si_3N_4$ for newly proposed Co/Ni composite salicide process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.75-76
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• 2007

Poly-Si Schottky barrier Thin Film Transistor (SB-TFT) is manufactured with erbium silicided source/drain. High quality poly-Si film was obtained by crystallizing the amorphous Si film with Excimer laser annealing (ELA) method. The fabricated poly-Si SB-TFT devices showed low leakage current and large on/off current ratio. Moreover, the electrical characteristics were considerably improved by 3% $H_2/N_2$ gas annealing, which is attributed to the reduction of trap states at the grain boundaries and interface trap states at gate oxide/poly-si channel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.195-196
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• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• Korean Journal of Materials Research
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• v.16 no.10
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• pp.656-662
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• 2006

We fabricated thermal evaporated 10 nm-$Ni_xCo_{1-x}$ (x=0.2, 0.5 and 0.8) /(poly)Si films to form nanothick cobalt nickel composite silicides by a rapid thermal annealing at $700{\sim}1100^{\circ}C$ for 40 seconds. A field emission scanning electron microscope and a micro-Raman spectrometer were employed for microstructure and silicon residual stress characterization, respectively. We observed self-aligned micro-pinholes on single crystal silicon substrates silicidized at $1100^{\circ}C$. Raman silicon peak shift indicates that the residual tensile strain of $10^{-3}$ in single crystal silicon substrates existed after the silicide process. We propose thermal stress from silicide exothermic reaction and high temperature silicidation annealing may cause the pinholes. Those pinholes are expected to be avoided by lowering the silicidation temperature. Our results imply that we may use our newly proposed composite silicides to induce the appropriate strained layer in silicion substrates.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• Journal of the Korean Ceramic Society
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• v.36 no.6
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• pp.604-610
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• 1999

Silicide layer structures and morphology degradation of the surface and interface of the silicide layers for he Co/refractory metal bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The CoSi-CoSi2 phase transition temperature is lower an morphology degradation of the silcide layer occurs more severely for the Co/refractorymetal bilayer on the P-doped polycrystalline Si substrate than on the single Si substrate. Also the final layer structure and the morphology of the films after silicidation annealing was found to depend strongly upon the interlayer metal. The layer structure after silicidation annealing of Co/Hf/doped-poly Si is Co-Hf alloy/polycrystalline CoSi2/poly Si substrate while that of Co/Nb is polycrystalline CoSi2/NbSi2/polycrystalline CoSi2/poly Si.

• Korean Journal of Materials Research
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• v.5 no.3
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• pp.324-332
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• 1995

전자빔 증착법을 사용하여 Ti과 Co를 Si(100) 단결정, 다결정 Si 및 Si$O_{2}$기판에 증착한 후 90$0^{\circ}C$에서 20초 급속 열처리하여, Co/Ti 이중박막으로부터의 실리사이드화 반응을 조사하였다. 단결정 시편의 경우 Ti의 두께를 5~6mm로 최소화함으로서 두께가 균일하고 기판과의 계면이 평탄하며 비저항이 낮고 열적 안정성이 높은 Co$Si_{2}$ 에피박막을 형성할 수 있었다. 그러나 다결정 시편에는 두께와 계면이 불균일하고 열적으로도 불안정한 다결정의 Co$Si_{2}$와 그 위에 두개의 Co-Ti-Si혼합층이 형성되었다. 한편 Si$O_{2}$ 우에 증착된 Co/Ti은 열처리를 하여도 확산하지 않고 그대로 남아 있어서, Co/Ti 이중박막의 Si$O_{2}$와의 반응성이 미약함을 보여 주었다.

• Journal of the Korean institute of surface engineering
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• v.32 no.6
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• pp.703-708
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• 1999

Silicides have been used extensively in ULSI logic device fabrication as contact materials for the active areas as well as the poly- Si gates. NiSi is a promising candidate for submicron device application due to less volume expansion, low formation temperature, little silicon consumption, and large stable processing temperature window. In this report, the microstructure of nickel silicides fabricated with a thermal evaporator has been investigated. We observed systematic transformation of Ni silicides of $Ni_2$Si, NiSi, $NiSi_2$, as annealing temperature increases. All the silicides have been identified by a X-ray diffractometer (XRD). The cross-sectional microstructure of silicides was examined by a transmission electron microscope (TEM) equipped with a energy dispersive spectrometer(EDS). The surface roughness of silicides was measured by scanning probe microscope(SPM). Although we observed thin oxide layer existed at the $Ni/NiSi_{x}$ interface, we fabricated successfully $550\AA$-thick planar Ni-monosilicide at the temperature range of$ 400~700^{\circ}C$.

• Journal of the Korean Ceramic Society
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• v.33 no.9
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• pp.1012-1018
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• 1996

To investigate the final structures and reactions of silicides a somewhat thick Ti monolayer Co monolayer and Co/Ti bilayer films were deposited on single Si(100) wafer by electron beam evaporation followed by heat treatment using RTA system in N2 ambient. TiO2 film formed between Ti and TiSi2 layers due to oxgen or moisture in the Ti monolayer sample. The final layer structure obtained after the silicidation heat-treatment of the Co/Ti bilayer sample turned out to be TiSi2/CoSi2/Ti-Co-Si alloy/CoSi2/Si sbustrate. This implies that imperfect layer inversion occurred due to the formation of Ti-Co-Si intermediate phase.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.234-237
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• 2002

The cobalt silicide was formed OH POly-Si/SiO$_2$/Si Substrates by the E-beam evaporation of Co metal and rapid thermal annealing method for the application of heating actuators. The most stable CoSi$_2$crystal was obtained at temperature of above $700^{\circ}C$ for 20 sec in $N_2$ambient. From the SEM observation, the thickness and diameter of the heating elements were about $1{\mu}{\textrm}{m}$ and $50{\mu}{\textrm}{m}$, respectively. Temperature resistance coefficient of heating elements was found to be about 0.0014($1/^{\circ}C$) with $30~35\Omega$ of resistance.