• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.10
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• pp.1935-1940
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• 2016

This paper proposes a phase-locked loop (PLL) to minimize the loop filter output voltage fluctuation by using a comparator including RC time constant circuits. The voltage variation of loop filter is inputted to RC time constant circuits which have two RC time constants, large and small. While a small RC time constant circuit quickly conveys the output voltage variation of loop filter, a large RC time constant circuit conveys slowly the output voltage variation of loop filter and its output looks like constant voltage. The output signal of the comparator controls the sub charge pump and reduces the input voltage variation of voltage-controlled oscillator (VCO). Therefore, the proposed PLL generates a phase noise reduced signal. It has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.697-699
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• 2017

A novel structure of phase locked loop (PLL) which has small size with D Flip-Flop and sub charge pump has been proposed. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Journal of Chest Surgery
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• v.42 no.4
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• pp.456-463
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• 2009

Background: Although the reports on re-operative coronary revascularization (redo-CABG) have increased, there are only limited reports on redo-CABG using arterial grafts. The aim of this study was to analyze the safety and feasibility of using various arterial grafts for redo-CABG. Material and Method: A consecutive series of patients who underwent 33 redo-CABGs from March 2001 to July 2008 were retrospectively reviewed. We performed conventional CABG in 17 patients, on-pump beating CABG in 7, off-pump CABG in 7 and minimally invasive direct coronary artery bypass in 2. The grafted that were used included 34 internal thoracic arteries (ITA), 14 radial arteries, 14 right gastroepiploic arteries and others. Arterial composite grafts were constructed in 26 patients. Of these, a previously patent in-situ left ITA was re-used as the in-flow of a composite graft in 10 patients. Result: No hospital deaths or major wound problems occurred. The post-operative complications included 2 myocardial infarctions (6%), 1 intra-aortic balloon pump insertion (3%), 5 cases of atrial fibrillation (15.1 %) and 3 neurologic complications (9.1%). The meanfollow-up duration was 31.1$\pm$22.7 months and the 3 year survival rate was 86.4%. There were 4 late deaths (2 cardiac deaths) and no recurrent angina during the follow-up period. Conclusion: Redo-CABG with using various arterial grafts is currently a safe, feasible procedure, but further investigation and long term follow-up are needed.