• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.88-93
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• 2003

IC 패키지 기술중 Underfilling 은 칩과 기판사이에 Encapsulant의 표면장력을 이용하여 주입하고 경화시킴으로써 전기적 기계적 보강력을 제공하는 기술로서 시스템 칩의 발전과 함께 차세대 패키징 기술중의 하나이다. 본 연구에서는 기존의 Underfilling 공정을 개선하여 충전시간을 획기적으로 줄일 수 있는 가압식 Underfilling 공정을 이용하여 차세대 반도체 패키징에 적용할 수 있는 가능성을 파악하였다. 이를 위하여 칩과 기판사이에 주입되고 경화되는 Encapsulant의 유동특성을 파악하였다. 가압식 Underfilling기술은 아직까지 상용화되지 않은 미래기술로써 효율적인 몰드 설계를 위하여 Encapsulant 종류에 따라 Gate 위치, Bump Pattern 및 개수, 칩과 기판 사이의 거리, Side Region에 따른 유동특성등의 파악이 중요하다. 본 연구에서는 $DEXTER^{TM}(US)$의 Encapsulant FP4511 을 사용하여 Cavity 내에 Void 를 없앨 수 있는 주입조건을 찾아내고 Underfilling 시간을 감소시킬 수 있는 모사를 진행하였다.

• Journal of Technology Innovation
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• v.28 no.4
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• pp.63-93
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• 2020

We suggest a new way of specifying the co-evolution of product and process technologies, and integrating it into one of the well-received technology intelligence tools - a technology radar. Cross impact analysis enables us to identify the core technologies of product-process co-evolution. Combining expert judgment with its results, we can clarify the technological co-evolution trajectory with mainstream as well as emerging core technologies. Reflecting these in the assessment process of a technology radar, we could improve reliance of the technology assessment process and technology portfolio. From the academic perspective, our research provides a point where the co-evolution theory encouners technology intelligence methods. Practically, strategic capability of future-preparedness and strategic management could improve by adopting our method based on our example of co-evolution of semiconductor product and process technologies.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.6
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• pp.443-453
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• 2017

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.673-674
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• 2012

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.8
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• pp.2158-2166
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• 1994

In order to understand the package crack emanating from the edge of leadframe after the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the M-integral and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the package crack are investigated taking into account the temperature dependence of the material properties, which simulates a more realistic condition. If the temperature dependence of the material properties is considered the result of analysis conforms with observations that the crack is kinked at between 50 and 65 degree. However, in case of constant material properties at the room temperature it is found that the J-integral is underestimated and the kink crack angle is different form the observation. The effects of the material properties and molding process temperature on J-integral and crack angle are less significant that the chip size for the cases considered here. It is suggested that the geometric factors such as ship size, leadframe size are to be well designed in order to prevent(or control) the occurrence and propagation of the package crack.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.30-41
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• 2023

With the aggressive down-scaling of advanced integrated circuits (ICs), electronic packages have become the bottleneck of both reliability and performance of whole electronic systems. In order to resolve the reliability issues, Institute of Electrical and Electronics Engineers (IEEE) laid down a roadmap on fault detection and diagnosis (FDD), thrusting the digital twin: a combination of reliability physics and artificial intelligence (AI). In this paper, we especially review research works regarding the signal-based FDD approaches on the electronic packages. We also discuss the research trend of FDD utilizing AI techniques.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.3
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• pp.37-42
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• 2022

Recently, the semiconductor package structures are becoming thinner and more complex. As the thickness decrease, interfacial delamination due to material mismatch can be further maximized, so the reliability of interface is a critical issue in industry field. Especially, the polymers, which are widely used in semiconductor packaging, are significantly affected by the temperature and moisture. Therefore, in this study, the delamination prediction at the interface of package structure was performed through finite element analysis considering the moisture absorption and desorption under the various temperature conditions. The material properties such as diffusivity and saturated moisture content were obtained from moisture absorption test. The hygro-swelling coefficients of each material were analyzed through TMA and TGA after the moisture absorption. The micro-shear test was conducted to evaluate the adhesion strength of each interface at various temperatures considering the moisture effect. The finite element analysis of interfacial delamination was performed that considers both deformation due to temperature and moisture absorption. Consequently, the interfacial delamination was successfully predicted in consideration of the in-situ moisture desorption and temperature behavior during the reflow process.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.51-63
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• 1999

The effects of high filler loading technique on the reliability of epoxy molding compound (EMC) as a microelectronic encapsulant was investigated. The method of high filler loading was established by the improvement of maximum packing fraction using the simplified packing model proposed by Ouchiyama, et al. With the maximum packing fraction of filler, the viscosity of EMC wart lowered and the flowability was improved. As the amount of filler in EMC increased, several properties such as internal stress and moisture absorption were improved. However, the adhesive strength with the alloy 42 leadframe decreased when the filler content was beyond the critical value. It was found that the appropriate content of filler was important to improve the reilability of EMC, and the optimum filler combination should be selected to obtain high reliable EMC filled with high volume fraction of filler.

• Journal of the Semiconductor & Display Technology
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• v.3 no.4
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• pp.33-37
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• 2004

As the high speed and high integration of semiconductor devices and the generation of heat increases resulted in the effective heat dissipation influences on the performance and lifetime of semiconductor devices. The heat resistance or heat spread function of EMC(epoxy molding compound) which protects these devices became one of very important factors in the evaluation of semiconductor chips. Recently, silica, alumina, AlN(aluminum nitride) powders are widely used as the fillers of EMC. The filler loading in encapsulants was high up to about 80 vol%. A high loading of filler was improved low water absorption, low stress, high strength, better flowability and high thermal conductivity. In this study, the thermal properties were investigated through thermal, mechanical and microstructure. Thermophysical properties were investigated by laser flash and differential scanning calorimeter(DSC). For detailed inspection of materials, the samples were examined by SEM.