Transactions of the Korean Society of Mechanical Engineers A (대한기계학회논문집A)

The Korean Society of Mechanical Engineers (대한기계학회)
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Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package

수치해석을 이용한 구리기둥 범프 플립칩 패키지의 열압착 접합 공정 시 발생하는 휨 연구

  • Kwon, Oh Young (Dept. of Manufacturing System and Design Engineering, Seoul Nat'l Univ. of Science and Technology) ;
  • Jung, Hoon Sun (Graduate School of NID Fusion Technology, Seoul Nat'l Univ. of Science and Technology) ;
  • Lee, Jung Hoon (Graduate School of NID Fusion Technology, Seoul Nat'l Univ. of Science and Technology) ;
  • Choa, Sung-Hoon (Graduate School of NID Fusion Technology, Seoul Nat'l Univ. of Science and Technology)
  • 권오영 (서울과학기술대학교 대학원 스마트생산융합시스템공학과) ;
  • 정훈선 (서울과학기술대학교 나노IT디자인 융합기술대학원) ;
  • 이정훈 (서울과학기술대학교 나노IT디자인 융합기술대학원) ;
  • 좌성훈 (서울과학기술대학교 나노IT디자인 융합기술대학원)
  • Received : 2016.08.08
  • Accepted : 2017.01.23
  • Published : 2017.06.01
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Abstract

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

반도체 플립칩 패키지에서 구리기둥 범프 기술은 미세 피치 및 높은 I/O 밀도로 인해 기존의 솔더 범프 접합 기술을 대체하는 중이다. 그러나 구리기둥 범프는 리플로우 접합 공정 사용 시, 구리 범프의 높은 강성으로 인해 패키지에 높은 응력을 초래한다. 따라서 최근에 플립칩 공정에서 발생하는 패키지의 높은 응력 및 휨을 감소시키기 위해 열압착 공정 기술이 시도되고 있다. 본 연구에서는 플립칩 패키지의 열압착 공정과 리플로우 공정에서 발생하는 휨에 대해 수치해석을 이용하여 분석하였다. 패키지의 휨 최소화를 위한 본딩 공정 조건 최적화를 위해 본딩 툴 및 스테이지의 온도, 본딩 압력에 대한 휨 영향을 검토하였다. 또한 칩과 기판의 면적 및 두께가 패키지의 휨에 주는 영향을 분석하였다. 이를 통해, 향후 미세피치 접합부 형성 시 휨 및 응력을 최소화하기 위한 가이드라인을 제시하고자 하였다.

Keywords

References

  1. Nam, H. W., 2004, "Robust Design and Thermal Fatigue Life Prediction of Anisotropic Conductive Film Flip Chip Package," Trans. Korean Soc. Mech. Eng. A, Vol. 28, No. 9, pp. 1408-1414. https://doi.org/10.3795/KSME-A.2004.28.9.1408
  2. Hsieh, M. C., Lee, C. C. and Hung, L. C., 2013, "Comprehensive Thermo-Mechanical Stress Analyses and Underfill Selection of Large Die Flip Chip BGA," IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 3, No. 7, pp. 1155-1162. https://doi.org/10.1109/TCPMT.2012.2232712
  3. Cheng, R., Wang, M., Kuo, R. H., Chen, E., Chuang, I. C., Pai, B., Chang, J. and Cheung, C., 2015, "FC Cu Pillar Package Development for Broad Market Applications," Proc. 65th Electron. Comp. Technol. Conf., pp. 609-614.
  4. Kim, M. S., Ko, Y. H., Bang, J. H. and Lee, C. W., 2012, "The Chip Bonding Technology on Flexible Substrate by Using Micro Lead-free Solder Bump," J. Microelectron. Packag. Soc., Vol. 19, No. 3, pp. 15-20. https://doi.org/10.6117/kmeps.2012.19.3.015
  5. Cassier, A., Zhao, L., Syed, A., Bezuk, S., Miller, W., Leong, A. and Slessor, M., 2014, "Reliable Testing of Cu Pillar Technology for Smart Devices," Chip Scale Review, Vol. 18, No. 5, pp. 22-27.
  6. Park, J., Kim, Y., Na, S., Kim, J., Lee, C. H. and Nicholls, L., 2015, "High Reliability Packaging Technologies and Process for Ultra Low k Flip Chip Devices," Proc. 65th Electron. Comp. Technol. Conf., pp. 1-6.
  7. Hsieh, M. C., Lee, C. C., Hung, L. C., Wang, V. and Perng, H., 2011, "Parametric Study for Warpage and Stress Reduction of Variable Bump Types in fcFBGA," Proc. 6th Inter. Microsys. Packag. Assemb. Circuits Technol. Conf., pp. 115-118.
  8. Kim, M. Y., Lim, S. K. and Oh, T. S., 2010, "Thermal Cycling and High Temperature Storage Reliabilities of the Flip Chip Joints Processed Using Cu Pillar Bumps," J. Microelectron. Packag. Soc, Vol. 17, No. 3, pp. 27-32.
  9. Hsieh, M. C., Lee, C. C. and Hung, L. C., 2013, "Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA," IEEE Trans. Compon. Packag. Manuf. Technol. Conf., Vol. 3, No. 1, pp. 61-70.
  10. Cheng, P. J., Wu, W. C., Wang, W. J. and Pai, T. M., 2015, "Challenge and Process Optimization of Thermal Compression Bonding with Non Conductive Paste," Proc. 65th Electron. Comp. Technol. Conf., pp. 484-489.
  11. Lin, L., Wang, J., Wang, L. and Zhang, W., 2015, "Stress Analysis and Parametric Studies for a Ultralow-k Chip in the Flip Chip Process," Proc. 16th Inter. Conf. Electron. Packag. Technol., pp. 689-693.
  12. Yang, H. G. and Joo, J. W., 2014, "Measurement and Evaluation of Thermal Expansion Coefficient for Warpage Analysis of Package Substrate," Trans. Korean Soc. Mech. Eng. A, Vol. 38, No. 10, pp. 1049-1056. https://doi.org/10.3795/KSME-A.2014.38.10.1049
  13. Addagarla, A. and Prasad, N. S., 2012, "Finite Element Analysis of Flip - Chip on Board (FCOB) Assembly During Reflow Soldering Process," J. Solder. Surf. Mt. Technol., Vol. 24, No. 2, pp. 92-99. https://doi.org/10.1108/09540911211214668
  14. Hsieh, M. C. and Tzeng, S. L., 2014, "Design and Stress Analysis for Fine Pitch Flip Chip Packages with Copper Column Interconnects," 15th International Conference on Electronic Packaging Technology(ICEPT), pp. 502-507.
  15. Zhang, J., Yuan, F. and Zhang, J., 2009, "Simulation Study on the Influences of the Bonding Parameters on the Warpage of Chip-on-glass Module with Nonconductive Film," J. Electron. Packag., Vol. 131, No. 4, pp. 041008-1-041008-5. https://doi.org/10.1115/1.4000361
  16. Lee, Y. C., Factor, B., Kao, C. L., Yannou, J. M. and Lee, C. C., 2013, "Copper Pillar Shape and Related Stress Simulation Studies in Flip Chip Packages," Euro. Microelec. Packag. Conf., pp. 1-5.
  17. Fu, J., Aldrete, M., Shah, M., Noveski, V. and Hsu, M., 2015, "Thermal Compression Bonding for Fine Pitch Solder Interconnects," Proc. 65th Electron. Comp. Technol. Conf., pp. 7-11.
  18. Au, K. Y., Che, F. X., Aw, J. L., Lin, J. K., Boehme, B. and Kuechenmeister, F., 2014, "Thermocompression Bonding Assembly Process and Reliability Studies of Cu Pillar Bump on Cu/Low-k Chip," Proc. 16th Electron. Packag. Technol. Conf., pp. 574-578.
  19. Che, F. X., Lin, J. K., Au, K. Y., Hsiao, H. Y. and Zhang, X., 2015, "Stress Analysis and Design Optimization for Low-k Chip With Cu Pillar Interconnection," IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 5, No. 9, pp. 1273-1283. https://doi.org/10.1109/TCPMT.2015.2461020
  20. Anand, L., 1982, "Constitutive Equations for the Rate-Dependent Deformation of Metals at Elevated Tempertures," ASME Journal of Eng. Mater. Tech., Vol. 105. No. 1, p.12.
  21. Hsieh, M. C., Lee, C. C. and Hung, L. C., 2012, "Reliability Assessments and Designs for Fine Pitch Flip Chip Packages with Cu Column Bumps," Proc. 7th Inter. Microsys. Packag. Assemb. Circuits Technol. Conf., pp. 280-283.
  22. Park, A. Y., Park, S. and Yoo, C. D., 2015, "Development of Inclined Conductive Bump for Flip-Chip Interconnection," IEEE Trans. Compon. Packag. Manuf. Technol., Vol. 5, No. 2, pp. 207-216. https://doi.org/10.1109/TCPMT.2014.2379264
  23. Smet, V., Huang, T. C., Kawamoto, S., Singh, B., Sundaram, V., Raj, P. M. and Tummala, R., 2015, "Interconnection Materials, Processes and Tools for Fine-pitch Panel Assembly of Ultra-thin Glass Substrates," Proc. 65th Electron. Comp. Technol. Conf., pp. 475-483.
  24. JEDEC Standard No. 22-B112A, 2009, "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature."
  25. Pan, C. A., Wu, M. Y., Lee, C. W., Lo, R., Wang, Y. P. and Hsiao, C. S., 2014, "TCBNCP Process Impact on Package Warpage Performance," Proc. 9th Inter. Microsys. Packag. Assemb. Circuits Technol. Conf., pp. 146-149.
  26. Li, M., Tian, D. W., Cheung, Y. M., Yang, L. and Lau, J. H., 2015. "A High Throughput and Reliable Thermal Compression Bonding Process for Advanced Interconnections," 2015 Electron. Comp. Technol. Conf., pp. 603-608.