• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.12
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• pp.1698-1704
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• 2018

This paper presents a implementation of a chaotic Lorenz system for data secure communication applications. Here we have used PIC18F family-based microcontroller to generate the chaotic signal, and simulated waveform patterns confirm that the chaotic behavior of the microcontroller based discrete time chaotic Lorenz system. There are three R-2R ladder type A/D converters have been implemented for conversion of direct microcontroller digital output into analog waveform, utilizing this specific microcontroller relevant to this experiment work, microcontroller ports B, C and D have been utilized for its time waveform outputs X, Y and Z respectively. XC8 compiler used for the compilation of the program. MATLAB and PROTEUS software platforms are used for simulation. Finally, chaotic time wave forms, 2D chaotic attractors were obtained and secure communication analog waveforms were also verified by experimental measurement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5C
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• pp.395-402
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• 2008

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.460-465
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• 2007

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.31-38
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• 2008

This paper describes sensor network system implementation for the IEEE 1451.2 standard which guarantees compatibilities between various wired sensors. The proposed system consists of the Network Capable Application Processor(NCAP) in the IEEE 1451.0, the Transducer Independent Interface(TII) in the IEEE 1451.2, the Transducer Electronic Data Sheet(TEDS) and sensors. The research goal of this study is to minimize and optimize system complexity for IC design. The NCAP is implemented using C language in personal computer environment. TII is used in the parallel port between PC and an FPGA application board. Transducer is implemented using Verilog on the FPGA application board. We verified the proposed system architecture based on the standards.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.3
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• pp.1-8
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• 2000

This paper presents a simulation model of the Quadrature detector to demodulate FSK signal, which is widely used in wireless paging system for its simple hardware implementation and economics of It fabrication. Quadrature detecter has nonlinear phase characteristic for changes linear changes of input signal frequency. So until now Quadrature detector system analysis remained a difficult problem and performance analysis has not been carried out adequately On these backgrounds, this paper presents the FSK signal demodulation process using Quadrature detector and optimal performance derived from digital simulation technique. First, PSN(Phase Shift Network) which is composed of analog RLC tank circuit is transformed into its equivalent digital transfer function using First-order-hold theorem. Though the demodulated outputs of the Quadrature detector for 4FSK are 4-level signals, only 2 comparators are used and it is shown that optimal performance can be obtained by choosing operation parameter Q value and threshold level decision which are proposed herein.