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http://dx.doi.org/10.6109/jkiice.2010.14.1.197

A Novel Third-Order Cascaded Sigma-Delta Modulator using Switched-Capacitor  

Ryu, Jee-Youl (부경대학교 전자컴퓨터정보통신학부)
Noh, Seok-Ho (안동대학교 전자공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.14, no.1, 2010 , pp. 197-204 More about this Journal
Abstract
This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.
Keywords
Switched-capacitor; Compensated switch configuration; Gain; Sigma-delta modulator;
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