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An I/Q Channel 12bit 40MS/s Pipeline A/D Converter with DLL Based Duty-Correction Circuit for WLAN  

Lee, Jae-Yong (페어차일드 코리아 반도체)
Cho, Sung-Il (인하대학교 전자공학과 정보전자 공동 연구소)
Park, Hyun-Mook (인하대학교 전자공학과 정보전자 공동 연구소)
Lee, Sang-Min (인하대학교 전자공학과 정보전자 공동 연구소)
Yoon, Kwang-Sub (인하대학교 전자공학과 정보전자 공동 연구소)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.33, no.5C, 2008 , pp. 395-402 More about this Journal
Abstract
In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.
Keywords
ADC(Analog-to-Digital converter); Pipeline; DLL(Delay locked loop); CMOS; Duty-correction;
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