• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.2
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• pp.302-312
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. Double frequency conversion and active tracking filter was used in order to suppress IF beat and image band, which results in reducing the interference between adjacent channels and multi-channels. The implemented digital TV tuner has excellent performance such as the wide dynamic range, good flatness in passing band, and low phase noise. The developed tuner is available to handle the digital and analogue television signal at the same time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1019-1024
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• 2007

In this paper, the 10bit 20MHz pipelined analog-to-digital converter that is able to apply to WLAN system was modeled for ADC design. Each blocks in converter such as sample and hold amplifier(SHA), comparator, multiplyng DAC(MDAC), and digital correction logic(DCL) was modeled. The pipelined ADC with these modeled blocks takes 1/50 less time than the one of simulation using HSPICE.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.1
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• pp.92-97
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• 2005

This paper discusses an intelligent digital redesign technique for designing a fuzzy pulse-width-modulated (PWM) control. First when we are given a well-designed fuzzy analog control, the equivalent digital control is intelligently redesigned. Using the similar technique we intelligently redesign the fuzzy PWM control from the intelligently redesigned fuzzy digital control. A stabilizability of the intelligently redesigned PWM control is rigorously analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.41-47
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• 2011

A novel digital instrumentation amplifier(DIA) converting universal signal inputs into 5V voltage-output for industry standard sensor signal processing was designed. The circuit consists of a commercial instrumentation amplifier, seven analog switches, two voltage references of 1.0V and -10.0V, and four resistors. The converting principle is the circuit reconstruction by switches for resistor values and reference voltages according to input signals. The simulation result shows that the DIA has a good output voltage characteristics of 0~5V for the input voltage of 0V~5V, 1V~5V, -10V~+10V, and 4mA~20mA. The nonlinearity error was less than 0.1% for the four type signal inputs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.799-804
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• 2012

To converter time information to digital information Time-to-Digital Converter(TDC) is designed by using analog delay elements. To obtain the temperature stable characteristics the circuit is designed and the operation of the designed circuit is confirmed by HSPICE. The characteristics variation of the designed delay element with temperature is from -0.18% to 0.126% compared to room temperature characteristics when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. Time difference is from -0.18% to 0.12% compared to room temperature characteristic when the temperature is varied from $-20^{\circ}C$ tp $70^{\circ}C$. The time difference is simulated when the digital output is 15. However the time difference is from -1.09% to 1.28% in the TDC using temperature non-stable analog delay elements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.91-96
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• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• Journal of Satellite, Information and Communications
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• v.7 no.3
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• pp.135-139
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• 2012

A digital controller can simply realize a complex operation algorithm and power control process which can not be applied by an analog circuit for a solar array regulator(SAR). The digital resistive control(DRC) makes an equivalent input impedance of the SAR be resistive characteristic. The resistance of the solar array varies largely in a voltage source region and slightly in a current source region. Therefore when the solar array regulator is controlled by the DRC, the Advanced Incremental Conductance MPPT Algorithm with a Variable Step Size(AIC-MPPT-VSS) is suitable. The AIC-MPPT-VSS, however, using small signal resistance and large signal resistance of the solar array can not limit the absolute value of the solar array power. In this paper, the solar array power limiter is suggested and the BUCK-BOOST type SAR which is fully controlled by the digital controller is verified by simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.4
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• pp.545-552
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• 2011

In this article, reference voltages in a general flash ADC are not obtained from a series of resistors but floating gates. When a behavior model simulation was performed in a pipelined ADC including the suggested flash ADC as a result of an ADC's overall function, it showed results that SNR is approximately 77 dB and resolution is 12 bit. And more than almost 90% showed INL within ${\pm}0.5$ LSB, and like INL, more than 90% showed DNL within ${\pm}0.5$ LSB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.25-34
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• 2005

In this paper, we analyzed and measured the electrical crosstalk characteristics of a triplex transceiver module for ethernet Passive optical networks(EPONS). And we improved the electrical crosstalk levels using Dummy ground lines with signal lines. The triplex transceiver module consists of a laser diode as a transmitter, a digital photodetector as a digital data receiver, and a analog photodetector as a community antenna television signal receiver. And there are integrated on silicon substrate. The digital receiver and analog receiver sensitivity have to meet -24 dBm at $BER=10^{-l2}$ and -7.7 dBm at 44 dB SNR. And the electrical crosstalk levels have to maintain less than -86 dB from DC to 3 GHz. From analysis and measurement results, the proposed silicon substrate structure that contains the Dummy ground line with $100\;{\mu}m$ space from signal lines and separates 4 mm among devices respectively, is satisfied the electrical crosstalk level compared to simple structure. This proposed structure can be easily implemented with design convenience and greatly reduced the silicon substrate size about $50\%$.