Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Incremental Delta-Sigma Analog to Digital Converter for Sensor

센서용 Incremental 델타-시그마 아날로그 디지털 변환기 설계

  • Jeong, Jinyoung (Dep. of Electronics & Communication Engineering, Hanyang Univ.) ;
  • Choi, Danbi (Dep. of Electronics & Communication Engineering, Hanyang Univ.) ;
  • Roh, Jeongjin (Dep. of Electronics & Communication Engineering, Hanyang Univ.)
  • 정진영 (한양대학교 전자통신공학과) ;
  • 최단비 (한양대학교 전자통신공학과) ;
  • 노정진 (한양대학교 전자통신공학과)
  • Received : 2012.03.15
  • Published : 2012.10.25
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Abstract

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

본 논문에서는 센서용 incremental 델타-시그마 아날로그 디지털 변환기를 설계 하였다. 회로는 크게 pre-amplifier, S & H (sample and hold) 회로, MUX와 델타-시그마 모듈레이터, 그리고 데시메이션 필터로 구성 되어 있다. 델타-시그마 모듈레이터는 3차 1-bit 구조이고 $0.18{\mu}m$ CMOS 공정을 사용 하였다. 설계된 회로는 테스트 결과 5 kHz 신호 대역에서 signal-to-noise and distortion ratio (SNDR)는 87.8 dB의 성능을 가지고, differential nonlinearity (DNL)은 ${\pm}0.25$ LSB (16-bit 기준), integral nonlinearity (INL)은 ${\pm}0.2$ LSB 이다. 델타-시그마 모듈레이터 전체 소비 전력은 $941.6{\mu}W$ 이다. 최종 16-bits 출력을 얻기 위하여 리셋을 인가하는 N cycle을 200 으로 결정하였다.

Keywords

References

  1. D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc. 1997
  2. 배성환, 이창기, "고정밀 저속 다중채널 아날로그- 디지털 변환기," 한국전자통신학회논문지 제3권 제 3호.
  3. J. Markus, J. Silva, G.C. Temes, "Theory and applications of incremental delta-sigma converters," IEEE Tran. on Circuits and Systems I, vol.51, no.4, pp.678-690, Apr. 2004. https://doi.org/10.1109/TCSI.2004.826202
  4. J. Markus, P. Deval, V. Quiquempoix, J. Silva, G.C. Temes, "Incremental Delta-sigma Structures for DC Measurement : an Overview," IEEE 2006 Custom Integrated Circuits Conference (CICC).
  5. S. Rabii and B. A. Wooley, The Design of Low Voltage, Low Power Sigma-Delta Modulators. KAP, 1999.
  6. D. Aksin, M. Al-Shyoukh, F. Maloberti , "A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage," IEEE 2005 Custom Integrated Circuits Conference (CICC).
  7. B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.
  8. J. Crols and M. Steyaert, "Switched-opamp: An approach to realize full CMOS switched -capacitor filters at very low power supply," IEEE J. Solid-State Circuits, vol. 29, pp. 936- 942, Aug. 1994. https://doi.org/10.1109/4.297698
  9. R. Gregorian, Introduction to CMOS op-amps and comparators. NewYork : John Wiley & Sons, Inc., 1999.
  10. MAXIM, "Histogram Testing Determines DNL and INL Errors"
  11. MAXIM, "INL/DNL Measurements for High- Speed Analog-to-Digital Converters(ADCs)"
  12. W. Kester, The Data Conversion Handbook, Analog Devices, Inc., 2005, pp. 303-316.
  13. R. J. Baker, W. L. Harry and E. B. David, CMOS Circuit Design, Layout, and Simulation, NY: IEEE Press, 1997.
  14. J. Roh, S. Byun, Y. Choi, H. Roh, Y. Kim, and J. Kwon, "A 0.9-V 60-W 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range," IEEE J. Solid-State Circuits, vol. 43, No. 2, pp. 361- 370, Feb. 2008. https://doi.org/10.1109/JSSC.2007.914266
  15. V. Peluso, M. Steyaert, and W. Sansen, "The Design of Low Voltage, Low Power Sigma-Delta Modulators," IEEE J. Solid-State Circuits, vol. 32, No. 7, pp. 943- 952, Jul. 1997. https://doi.org/10.1109/4.597284
  16. J. Liang, D.A. Johns, "A Frequency-Scalable 15-bit Incremental ADC for Low Power Sensor Applications", IEEE International Symposium on Circuits and Systems, May 30th -- Jun. 2nd, 2010, Paris, France, pp. 2418-2421