• Title/Summary/Keyword: 드레인유도장벽감소

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Analysis of Threshold Voltage and DIBL Characteristics for Double Gate MOSFET Based on Scaling Theory (스켈링 이론에 따른 DGMOSFET의 문턱전압 및 DIBL 특성 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.145-150
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    • 2013
  • This paper has presented the analysis for threshold voltage and drain induced barrier lowering among short channel effects occurred in subthreshold region for double gate(DG) MOSFET as next-generation devices, based on scaling theory. To obtain the analytical solution of Poisson's equation, Gaussian function has been used as carrier distribution to analyze closely for experimental results, and the threshold characteristics have been analyzed for device parameters such as channel thickness and doping concentration and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold characteristics. As a result to apply scaling theory, we know the threshold voltage and drain induced barrier lowering are changed, and the deviation rate is changed for device parameters for DGMOSFET.

Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 도핑분포함수에 따른 DIBL)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2643-2648
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    • 2015
  • This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

Effect of Channel Length and Drain Bias on Threshold Voltage of Field Enhanced Solid Phase Crystallization Polycrystalline Thin Film Transistor on the Glass Substrate (자계 유도 고상결정화를 이용한 다결정 실리콘 박막 트랜지스터의 채널 길이와 드레인 전압에 따른 문턱 전압 변화)

  • Kang, Dong-Won;Lee, Won-Kyu;Han, Sang-Myeon;Park, Sang-Geun;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.1263-1264
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    • 2007
  • 자계 유도 고상결정화(FESPC)를 이용하여 제작한 다결정실리콘(poly-Si) 박막 트랜지스터(TFT)는 비정질 실리콘 박막 트랜지스터(a-Si:H TFT)보다 뛰어난 전기적 특성과 우수한 안정성을 지닌다. $V_{DS}$ = -0.1 V에서 채널 폭과 길이가 각각 $5\;{\mu}m$, $7\;{\mu}m$인 P형 TFT의 이동도(${\mu}$)와 문턱 전압($V_{TH}$)은 각각 $31.98\;cm^2$/Vs, -6.14 V 이다. FESPC TFT는 일반 poly-Si TFT에 비해 채널 내 결정 경계 숫자가 많아서 상대적으로 열악한 특성을 가진다. 채널 길이 $5\;{\mu}m$인 TFT의 $V_{TH}$는 채널 길이 $18\;{\mu}m$ 소자의 $V_{TH}$보다 1.36V 작지만, 일반적으로 큰 값이다. 이 현상은 채널에 다수의 결정 경계가 존재하고, 수평 전계가 크기 때문이다. 수평 전계가 증가하면, 결정 경계의 전위 장벽 높이가 감소하게 되는데, 이는 DIGBL 효과이다. ${\mu}$의 증가에 따라서, 드레인 전류가 증가하고 $V_{TH}$은 감소한다. 활성화 에너지($E_a$)는 드레인 전압과 결정 경계의 수에 따라 변하는데, 드레인 전압이 크거나 결정 경계의 수가 감소하면 $E_a$는 감소한다. $E_a$가 감소하면 $V_{TH}$가 감소한다. 유리기판 위의 FESPC를 이용한 P형 poly-Si TFT의 $V_{TH}$는 채널의 길이와 $V_{DS}$에 영향을 받는다. 증가한 수평 전계가 결정 경계에서 에너지 장벽을 낮추는 효과를 일으키기 때문이다.

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Dependence of Drain Induced Barrier Lowering for Doping Profile of Channel in Double Gate MOSFET (이중게이트 MOSFET에서 채널내 도핑분포에 대한 드레인유기장벽감소 의존성)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.9
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    • pp.2000-2006
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    • 2011
  • In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.

Analysis of Subthreshold Characteristics for Double Gate MOSFET using Impact Factor based on Scaling Theory (스켈링이론에 가중치를 적용한 DGMOSFET의 문턱전압이하 특성 분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.2015-2020
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    • 2012
  • The subthreshold characteristics has been analyzed to investigate the effect of two gate in Double Gate MOSFET using impact factor based on scaling theory. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. The potential distribution was used to investigate the short channel effects such as threshold voltage roll-off, subthreshold swings and drain induced barrier lowering by varying impact factor for scaling factor. The impact factor of 0.1~1.0 for channel length and 1.0~2.0 for channel thickness are used to fit structural feature of DGMOSFET. The simulation result showed that the subthreshold swings are mostly effected by impact factor but are nearly constant for scaling factors. And threshold voltage roll-off and drain induced barrier lowering are also effected by both impact factor and scaling factor.

SPICE Model of Drain Induced Barrier Lowering in Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET (무접합 원통형 MOSFET에 대한 드레인 유도 장벽 감소의 SPICE 모델)

  • Jung, Hak Kee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.5
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    • pp.278-282
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    • 2018
  • We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

Analysis of Threshold Voltage Roll-Off and Drain Induced Barrier Lowering in Junction-Based and Junctionless Double Gate MOSFET (접합 및 무접합 이중게이트 MOSFET에 대한 문턱전압 이동 및 드레인 유도 장벽 감소 분석)

  • Jung, Hak Kee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.2
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    • pp.104-109
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    • 2019
  • An analytical threshold voltage model is proposed to analyze the threshold voltage roll-off and drain-induced barrier lowering (DIBL) for a junction-based double-gate (JBDG) MOSFET and a junction-less double-gate (JLDG) MOSFET. We used the series-type potential distribution function derived from the Poisson equation, and observed that it is sufficient to use n=1 due to the drastic decrease in eigenvalues when increasing the n of the series-type potential function. The threshold voltage derived from this threshold voltage model was in good agreement with the result of TCAD simulation. The threshold voltage roll-off of the JBDG MOSFET was about 57% better than that of the JLDG MOSFET for a channel length of 25 nm, channel thickness of 10 nm, and oxide thickness of 2 nm. The DIBL of the JBDG MOSFET was about 12% better than that of the JLDG MOSFET, at a gate metal work-function of 5 eV. It was also found that decreasing the work-function of the gate metal significantly reduces the DIBL.

Impact of Remanent Polarization and Coercive Field on Threshold Voltage and Drain-Induced Barrier Lowering in NCFET (negative capacitance FET) (NCFET (negative capacitance FET)에서 잔류분극과 항전계가 문턱전압과 드레인 유도장벽 감소에 미치는 영향)

  • Hakkee Jung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.1
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    • pp.48-55
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    • 2024
  • The changes in threshold voltage and DIBL were investigated for changes in remanent polarization Pr and coercive field Ec, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when Pr decreases and Ec increases, and the threshold voltage is also maintained constant when the Pr/Ec is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to Pr/Ec, so the DIBL greatly changes for Pr/Ec. In other words, when Pr/Ec=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO2 thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the Pr/Ec is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the Pr and Ec of ferroelectric.