• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.325-330
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• 2012

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel structure and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model. Resultly, DIBL has been greatly changed for channel structure and doping concentration.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.888-891
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping intensity.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.878-881
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• 2011

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel thickness and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.213.2-213.2
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• 2015

모바일 기기의 성장세로 인해 낸드 플래시 메모리에 대한 수요가 급격히 증가하면서 높은 집적도의 소자에 대한 요구가 커지고 있다. 그러나 기존의 MOSFET 구조의 소자는 비례 축소에 의한 게이트 누설 전류, 셀간 간섭, 단 채널 효과 같은 여러 어려움에 직면해 있다. 특히 트윈 실리콘 나노 와이어 전계 효과 트랜지스터 (TSNWFETs)는 소자의 크기를 줄이기 쉬우며 게이트 비례 축소가 용이하여 차세대 메모리 소자로 각광받고 있다. 그러나 TSNWFETs의 공정 방법과 실험적인 전기적 특성에 대한 연구는 많이 이루어 졌지만, TSNWFETs의 전기적 특성에 대한 이론적인 연구는 많이 진행되지 않았다. 본 연구는 직경의 크기가 다른 나노 와이어를 사용한 TSNWFETs의 전기적 특성에 대해 이론적으로 계산하였다. TSNWFETs과 실리콘 나노 와이어를 사용하지 않은 전계 효과 트랜지스터(FET)를 3차원 시뮬레이션 툴을 이용하여 계산하였다. TSNWFETs와 FETs의 드레인 전류와 문턱전압 이하 기울기, 드레인에 유기된 장벽의 감소 값, 게이트에 유기된 드레인 누설 전류 값을 이용하여 전류-전압 특성을 계산하였다. 이론적인 결과를 분석하여 TSNWFETs의 스위칭 특성과 단 채널 효과를 최소화하는 특성 및 전류 밀도를 볼 수 있었으며, 나노 와이어의 직경이 감소하면 증가하는 드레인에 유기된 장벽의 감소를 볼 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.2000-2006
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• 2011

In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.3
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• pp.579-584
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• 2012

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET. The DIBL is very important short channel effects as phenomenon that barrier height becomes lower since drain voltage influences on potential barrier of source in short channel. The analytical potential distribution of Poisson equation, validated in previous papers, has been used to analyze DIBL. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. The change of DIBL has been investigated for device parameters such as channel thickness, oxide thickness and channel doping concentration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.10
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• pp.2305-2309
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• 2010

In this paper, the variations of threshold voltage characteristics for ratio of channel length and thickness have been alanyzed for DG(Double Gate)MOSFET having top gate and bottom gate. Since the DGMOSFET has two gates, it has advantages that contollability of gate for current is nearly twice and SCE(Short Channel Effects) shrinks in nano devices. The channel length and thickness in MOSFET determines device size and extensively influences on SCEs. The threshold voltage roll-off, one of the SCEs, is large with decreasing channel length. The threshold voltage roll-off and drain induced barrier lowing have been analyzed with various ratio of channel length and thickness for DGMOSFET in this study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1463-1469
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• 2012

This paper has presented the influence of scaling theory on short channel effects of double gate(DG) MOSFET in subthreshold region. In the case of conventional MOSFET, to preserve constantly output characteristics,current and switching frequency have been analyzed based on scaling theory. To analyze the results of application of scaling theory for short channel effects of DGMOSFET, the changes of threshold voltage, drain induced barrier height and subthreshold swing have been observed according to scaling factor. The analytical potential distribution of Poisson equation already verified has been used. As a result, it has been observed that threshold voltage among short channel effects is grealty changed according to scaling factor. The best scaling theory for DGMOSFET has been explained as using modified scaling theory, applying weighting factor reflected the influence of two gates when scaling theory has been applied for channel length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.19-25
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• 2008

In this study, we fabricated Organic Thin Film Transistors(OTFTs) with $C_{60}$ hole injection layer between organic semiconductor(pentacene) and metal electrode, and we compared the electrical characteristics of OTFTs with/without $C_{60}$. When the $C_{60}$ hole injection layer was introduced, the mobility and the threshold voltage were improved from 0.298 $cm^2/V{\cdot}s$ and -13.3V to 0.452 $cm^2/V{\cdot}s$ and -10.8V, and the contact resistance was also reduced. When the $C_{60}$ is inserted, the hole injection was enhanced because the $C_{60}$ prevent the unwanted chemical reaction between pentacene and Au. Furthermore, we fabricated the OTFTs using Al as their electrodes. When the OTFTs were made by only aluminum electrode, the channel were not mostly made because of the high hole injection barrier between pentacene and aluminum, but when the $C_{60}$ layer with an optimal thickness was applied between aluminum and pentacene, the device performances were obviously enhanced because of the vacuum energy level shift of Al and the consequent decrease of the hole injection barrier which was induced by the interface dipole formation between $C_{60}$ and Al. The mobility and $I_{ON}/I_{OFF}$ current ratio of OTFT with $C_{60}/Al$ electrode were 0.165 $cm^2/V{\cdot}s$ and $1.4{\times}10^4$ which were comparable with the normal Au electrode OTFT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.5-12
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• 2005

The device performance of nano-scale center-channel (CC) double-gate (DG) MOSFET structure was investigated by numerically solving coupled Schr$\"{o}$dinger-Poisson and current continuity equations in a self-consistent manner. The CC operation and corresponding enhancement of current drive and transconductance of CC-NMOS are confirmed by comparing with the results of DG-NMOS which are performed under the condition of 10-80 nm gate length. Device optimization was theoretically performed in order to minimize the short-channel effects in terms of subthreshold swing, threshold voltage roll-off, and drain-induced barrier lowering. The simulation results indicate that DG-MOSFET structure including CC-NMOS is a promising candidates and quantum-mechanical modeling and simulation calculating the coupled Schr$\"{o}$dinger-Poisson and current continuity equations self-consistently are necessary for the application to sub-40 nm MOSFET technology.