• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.1 s.307
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• pp.39-44
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• 2006

Pattern noise in the Delta-Sigma modulator is a well Known phenomenon that intrigued many circuit designers. These noise appear as the modulator output falls into a cyclic mode of operation. This paper addresses the dependence of these tone signal upon the system topologies. Among the four well known single-stage DSM topologies, namely Cascade of Integrators with Feedback Form(CIFB), Cascade of Integrators with Feedforward Form(CIFF), Cascade of Resonators with Feedback Form(CRFB), and Cascade of Resonators with Feedforward Form(CRFF), resonator type DSMs turn out to be more susceptible to the pattern noise than the integrator type. Noise transfer functions of the investigated topologies are also presented.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.148-158
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• 2012

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S & H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a $0.18{\mu}m$ CMOS technology. The designed circuit show that the modulator achieves 87.8 dB signal-to-noise and distortion ratio (SNDR) over a 5 kHz signal bandwidth and differential nonlinearity (DNL) of ${\pm}0.25$ LSB, integral nonlinearity (INL) of ${\pm}0.2$ LSB. Power consumption of delta-sigma modulator is $941.6{\mu}W$. It was decided that N cycles are 200 clock for 16-bits output.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.405-408
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure, which is a type of an IIR filter. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.6-12
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• 2010

A sigma-delta modulator based class-D audio amplifier is presented. Parallel digital input is serialized to two-bit output by a fourth-order digital sigma-delta noise shaper. The output of the digital sigma-delta noise shaper is applied to a fourth-order analog sigma-delta modulator whose three-level output drives power switches. The pulse density modulated (PDM) output of the power switches is low-pass filtered by an LC-filter. The PDM output of the power switches is fed back to the input of the analog sigma-delta modulator. The first integrator of the analog sigma-delta modulator is a hybrid of continuous-time (CT) and switched-capacitor (SC) integrator. While the sampled input is applied to SC path, the continuous-time feedback signal is applied to CT path to suppress the noise of the PDM output. The class-D audio amplifier is fabricated in a standard $0.13-{\mu}m$ CMOS process and operates for the signal bandwidth from 100-Hz to 20-kHz. With 4-${\Omega}$ load, the maximum output power is 18.3-mW. The total harmonic distortion plus noise and dynamic range are 0.035-% and 80-dB, respectively. The modulator consumes 457-uW from 1.2-V power supply.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.906-909
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• 2006

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented in a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.4
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• pp.707-714
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• 2012

After a single-stage, second-order, multiple-feedback ${\Delta}-{\Sigma}$ modulator and a two-stage, second-order MASH ${\Delta}-{\Sigma}$ modulator were analyzed and simulated using Simulink and Matlab and their characteristics were compared, the following result was obtained: 1) The two ${\Delta}-{\Sigma}$ modulators do not have group delay distortion. 2) The characteristics of the noise shaping are nearly identical. As a result of the noise shaping, the power spectral densities have slope of 40 dB/dec. 3) There was no spurious tone. 4) The input range of the two modulators is from -1 to +1 in common. 5) Because the output of the two-stage MASH modulator is 2-bits (4-levels), design of frequency dividers and charge pumps of PLL are more demanding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.197-204
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• 2010

This paper proposes a new body-effect compensated switch configuration for low voltage and low distortion switched-capacitor (SC) applications. The proposed circuit allows rail-to-rail switching operation for low voltage SC circuits and has better total harmonic distortion than the conventional bootstrapped circuit by 19 dB. A 2-1 cascaded sigma-delta modulator is provided for performing the high-resolution analog-to-digital conversion on audio codec in a communication transceiver. An experimental prototype for a single-stage folded-cascode operational amplifier (opamp) and a 2-1 cascaded sigma-delta modulator has been implemented m a 0.25 micron double-poly, triple-metal standard CMOS process with 2.7 V of supply voltage. The 1% settling time of the opamp is measured to be 560 ns with load capacitance of 16 pF. The experimental testing of the sigma-delta modulator with bit-stream inspection and analog spectrum analyzing plot is performed. The die size is $1.9{\times}1.5\;mm$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2649-2655
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• 2015

While the oversampling sigma-delta ADCs are known to have high resolution, they often suffer from SNDR losses when operated at a very high data clock. This paper presents a design and implementation of a decimation filter that provides minimum distortion at passband for high-speed sigma-delta ADC. The proposed digital decimation filter employs a butterworth structure. To evaluate the performance of the proposed decimation filter, we implemented a 1-bit, third-order, OSR=64 sigma-delta modulator followed by the proposed decimation filter. Using the simulation ad measurement, we compared the performance of the proposed decimation filter with a conventional CIC(cascaded integrator comb) decimation filter, which is commonly used in most sigma-delta ADCs. The measurement results show that the proposed decimation filter presents substantially lower distortion at passband and thus can provide must higher SNDR.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.