• Title/Summary/Keyword: 공정 파라미터

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Design of A CMOS Composite Cell Analog Multiplier (CMOS 상보형 구조를 이용한 아날로그 멀티플라이어 설계)

  • Lee, Geun-Ho;Choe, Hyeon-Seung;Kim, Dong-Yong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.37 no.2
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    • pp.43-49
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    • 2000
  • In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

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A Reference Spur Suppressed PLL with Two-Symmetrical Loops (기준 신호 스퍼의 크기를 줄인 두 개의 대칭 루프를 가진 위상고정루프)

  • Choi, Hyun-Woo;Choi, Young-Shig
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.5
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    • pp.99-105
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    • 2014
  • A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

A Study on the Design of Tolerance for Process Parameter using Decision Tree and Loss Function (의사결정나무와 손실함수를 이용한 공정파라미터 허용차 설계에 관한 연구)

  • Kim, Yong-Jun;Chung, Young-Bae
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.39 no.1
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    • pp.123-129
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    • 2016
  • In the manufacturing industry fields, thousands of quality characteristics are measured in a day because the systems of process have been automated through the development of computer and improvement of techniques. Also, the process has been monitored in database in real time. Particularly, the data in the design step of the process have contributed to the product that customers have required through getting useful information from the data and reflecting them to the design of product. In this study, first, characteristics and variables affecting to them in the data of the design step of the process were analyzed by decision tree to find out the relation between explanatory and target variables. Second, the tolerance of continuous variables influencing on the target variable primarily was shown by the application of algorithm of decision tree, C4.5. Finally, the target variable, loss, was calculated by a loss function of Taguchi and analyzed. In this paper, the general method that the value of continuous explanatory variables has been used intactly not to be transformed to the discrete value and new method that the value of continuous explanatory variables was divided into 3 categories were compared. As a result, first, the tolerance obtained from the new method was more effective in decreasing the target variable, loss, than general method. In addition, the tolerance levels for the continuous explanatory variables to be chosen of the major variables were calculated. In further research, a systematic method using decision tree of data mining needs to be developed in order to categorize continuous variables under various scenarios of loss function.

A Study on Optimal PID Controller Design Ensure the Absolute Stability (절대안정도를 보장하는 최적 PID 제어기 설계에 관한 연구)

  • Cho, Joon-Ho
    • Journal of Convergence for Information Technology
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    • v.11 no.2
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    • pp.124-129
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    • 2021
  • In this paper, an optimal controller design that guarantees absolute stability is proposed. The order of application of the thesis determines whether the delay time is included, and if the delay time is included, the delay time is approximated through the Pade approximation method. Then, the open loop transfer function for the process model and the controller transfer function is obtained, and the absolute stability interval is calculated by the Routh-Hurwitz discrimination method. In the last step, the optimal Proportional and Integral and Derivative(PID) control parameter value is calculated using a genetic algorithm using the interval obtained in the previous step. As a result, it was confirmed that the proposed method guarantees stability and is superior to the existing method in performance index by designing an optimal controller. If we study the compensation method for the delay time in the future, it is judged that better performance indicators will be obtained.

Switching and Leakage-Power Suppressed SRAM for Leakage-Dominant Deep-Submicron CMOS Technologies (초미세 CMOS 공정에서의 스위칭 및 누설전력 억제 SRAM 설계)

  • Choi Hoon-Dae;Min Kyeong-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.3 s.345
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    • pp.21-32
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    • 2006
  • A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.

A UTMI-Compatible USB2.0 Transceiver Chip Design (UTMI 표준에 부합하는 USB2.0 송수신기 칩 설계)

  • Nam Jang-Jin;Kim Bong-Jin;Park Hong-June
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.5 s.335
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    • pp.31-38
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    • 2005
  • The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

A Study on Spectra of Laser Induced Flourescence in Phantom of N-propyl-N,N-dimethylethanolamine (N-propyl-N,N-dimethylethanolamine의 Phantom에서 Laser Induced Fluorescence의 스펙트라에 관한 연구)

  • Kim, Ki-Jun;Lee, Joo-Ho;Lee, Joo-Youb;Sung, Wan-Mo
    • Journal of the Korean Applied Science and Technology
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    • v.32 no.2
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    • pp.330-338
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    • 2015
  • The influences of fluorescence, scattering, and flocculation in turbid material by light scattering of N-propyl-N,N-dimethylethanolamine, fluorescence agent and absorption agent were interpreted for the scattered fluorescence intensity and wavelength. They have been studied the molecular properties by the spectroscopy of laser induced fluorescence (LIF) and flocculation. The effects of optical properties in scattering media have been found by the optical parameters(${\mu}_s$, ${\mu}_a$, ${\mu}_t$). Flocculation is an important step in many solid-liquid separation processes and is widely used. When two particles approach each other, interactions of several colloid particles can come into play which may have major effect on the flocculation and LIF process. The values of scattering coefficient ${\mu}_s$ are large by means of the increasing scattering of scatterer, The values have been found that the slope decays exponentially as a function of concentration from laser source to detector by our experimental result. It may also aid in designing the best model for oil chemistry, bio-pharmaceutical, laser medicine and application of medical engineering on LIF and coagulation in particle transport mode.

Study on the Adsorption of Antibiotics Trimethoprim in Aqueous Solution by Activated Carbon Prepared from Waste Citrus Peel Using Box-Behnken Design (박스-벤켄 설계법을 이용한 폐감귤박 활성탄에 의한 수용액 중의 항생제 Trimethoprim의 흡착 연구)

  • Lee, Min-Gyu;Kam, Sang-Kyu
    • Korean Chemical Engineering Research
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    • v.56 no.4
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    • pp.568-576
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    • 2018
  • In order to investigate the adsorption characteristics of the antibiotics trimethoprim (TMP) by activated carbon (WCAC) prepared from waste citrus peel, the effects of operating parameters on the TMP adsorption were investigated by using a response surface methodology (RSM). Batch experiments were carried out according to a four-factor Box-Behnken experimental design with four input parameters : concentration ($X_1$: 50-150 mg/L), pH ($X_2$: 4-10), temperature ($X_3$: 293-323 K), adsorbent dose ($X_4$: 0.05-0.15 g). The experimental data were fitted to a second-order polynomial equation by the multiple regression analysis and examined using statistical methods. The significance of the independent variables and their interactions was assessed by ANOVA and t-test statistical techniques. Statistical results showed that concentration of TMP was the most effective parameter in comparison with others. The adsorption process can be well described by the pseudo-second order kinetic model. The experimental data of isotherm followed the Langmuir isotherm model. The maximum adsorption amount of TMP by WCAC calculated from the Langmuir isotherm model was 144.9 mg/g at 293 K.

Ultra Wideband CPW Baluns Having Multistage Wilkinson Structure (다단 윌킨슨 구조의 초광대역 CPW 발룬)

  • Lim Jong-Sik;Park Ung-Hee;Jeong Yong-Chae;Ahn Dal;Oh Seong-Min;Koo Jae-Jin;Kim Kwang-Soo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.9 s.112
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    • pp.811-820
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    • 2006
  • Ultra wideband CPW batons are proposed in this paper. The proposed talons are consisted of ultra wideband multi-stage Wilkinson dividers and 'X'-shaped $180^{\circ}$ out-of-phase generator. Bottom-bridges and via-holes are used to connect CPW ground lines instead of the conventional air-bridges which require troublesome manual working in fabrication with HMIC(Hybrid Microwave Integrated Circuits) substrates. The proposed CPW batons have ultra wideband of 3 or $10(=F_{figh}/F_{low})$ theoretically, the wideband characteristics and S-parameters of the basis Wilkinson divider are directly converted to those of the proposed batons. The proposed batons are so compact and small compared to the conventional Wilkinson batons because no additional area for out-of-phase section is required. So the size of the proposed batons is exactly the same as that of the basis Wilkinson dividers. As examples, 3-stage and 7-stage wideband Wilkinson dividers are converted to the proposed batons. Their measured operating bandwidth are $1\sim3GHz$ and $0.8\sim5GHz$, respectively, with excellent matching, isolation and power division performances. The measured magnitude and phase balance errors are ${\pm}0.5dB\;and\;0.45\;dB,\;and\;{\pm}5^{\circ}\;and\;{\pm}10^{\circ}C$ over $1\sim3GHz\;and\;0.8\sim5GHz$, respectively.

Operating Conditions Proposal of Bandgap Circuit at Cryogenic Temperature for Signal Processing of Infrared Detector and a Performance Analysis of a Manufactured Chip (적외선 탐색기 신호처리를 위한 극저온 밴드갭 회로 동작 조건 제안 및 제작된 칩의 성능 분석)

  • Kim Yon Kyu;Kang Sang-Gu;Lee Hee-Chul
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.12
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    • pp.59-65
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    • 2004
  • A stable reference voltage generator is necessary to the infrared image signal readout circuit(ROIC) to improve noise characteristics of signal originated from infrared devices, that is, to gain good images. In this paper, bandgap circuit operating at cryogenic temperature of 77K for Infrared image ROIC(readout integrated circuit) was first made. It demonstrates practical use possibility through taking measurements and estimations. Bandgap circuit is a representative voltage reference circuit. Most of bandgap reference circuits which are presented so far operate at room temperature, and their characteristic are not suitable for infrared image ROIC operating at liquid nitrogen temperature, 77K. To design bandgap circuit operating at cryogenic temperature, suitable circuit is selected and the parameter characteristics of used devices as temperature change are seen by a theoretical study and fitted at liquid temperature with considering such characteristics. This circuit has been fabricated in the Hynix 0.6um standard CMOS process, and the output voltage measured shows that the stability is 1.042±0.0015V over the temperature range of 60K to 110K and is better than bandgap circuits operated at room temperature.