1 |
K. Agarwal, H. Li, and K. Roy, 'A bit line leakage compensation scheme for low-voltage SRAM's,' IEEE Journal of Solid-State Circuits, vol.36, no.5, pp.726-734, May 2001
DOI
ScienceOn
|
2 |
H. Choi, H. Choi, K. Kang, D. Kwak, D. Kim, D. Kim, and K. Min, 'Leakage and Switching Power Saving Scheme For Low-Power SRAMs in sub-70nm Leakage-Dominant VLSI Era,' 제12회 한국반도체학술대회 논문집, vol.1, pp.497-498, Feb. 24-25, 2005
|
3 |
K. Kanda, T. Miyazaki, K. Min, H. Kawaguchi, and T. Sakurai, 'Two Orders of Magnitude Reduction of Low Voltage SRAM's by Row-by-Row Dynamic VDD Control (RDDV) Scheme,' Proceedings of IEEE International ASIC/SOC Conference, pp.381-385, Rochester in USA, September 2002
|
4 |
Berkeley predictive technology model web site: http://www-device.eecs.berkeley.edu/-ptm
|
5 |
S. Hattori and T. Sakurai, '90% write power saving SRAM using sense-amplifying memory cell,' Symposium on VLSI Circuits, pp.46-47, Kyoto in Japan, June 2002
DOI
|
6 |
K. Min, K. Kanda, and T. Sakurai, 'Row-by-Row switching Source-Line Voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V- SRAM's,' International Symposium on Low Power Electronics and Design, pp.66-71, Seoul in Korea, August 2003
|
7 |
S. Borkar, 'Design challenges of technology scaling,' IEEE Micro, vol.19, no. 4, pp, 23-29, July 1999
DOI
ScienceOn
|
8 |
T. Sakurai, 'Perspectives on power-aware electronics,' IEEE International Solid-State Circuits Conference, pp.26-29, San francisco in USA, February 2003
DOI
|