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JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (IEIE)

  • Bimonthly
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)

Aim & Scope

Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in every aspect of the integrated circuit technology, i.e., VLSI fabrication process technology, VLSI device technology, VLSI circuit design and other novel applications of this mass production technology. When IC was invented, these people worked together in one place. However, as the field of IC expanded, our individual knowledge became narrower, creating different branches in the technical society, which has made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to go backwards gathering people involved in all VLSI technology in one place. Vision Statement Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in wider scope of the integrated circuit technology, i.e., VLSI fabrication process technology, device technology, circuit design, packaging, test and other novel applications of this ever scaling technology. When IC was invented, these people worked together in one place, and understood every details of the flow from bare silicon to package testing. However, as the IC evolves with Moore’s curve, in-depth knowledge content has exploded, and our individual expertise has to become narrowed down. As a result, different branches in the technical society were created, and have made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to break the knowledge barrier, by providing communication channel for people working in relevant VLSI technology in common subject “Device & Design Integration”. Treaties on core technology that will affect the device including CMOS and MEMS devices, from the substrate to gate fabrication and its characterization and analysis are our major focus. The other focus is how to make the device function in a system and its verification the design. This device & design forum should provide better use of the other information and enhance the overall VLSI technology, eventually serving better to create more efficient devices and systems.

https://mc.manuscriptcentral.com/jsts-ieek KSCI KCI SCOPUS SCI SCIE

Volume 7 Issue 1

  1. Sim, Jae-Yoon 1
    https://doi.org/10.5573/JSTS.2007.7.1.001 PDF KSCI
    In recent few years, low-power electronics has been a leading drive for technology developments nourished by rapidly growing market share. Mobile DRAM, as a fundamental block of hand-held devices, is now becoming a product developed by limitless competition. To support application specific mobile features, various new power-reduction schemes have been proposed and adopted by standardization. Tightened power budget in battery-operated systems makes conventional schemes not acceptable and increases difficulty of the circuit design. The mobile DRAM has successfully moved down to 1.5V era, and now it is about to move to 1.2V. Further voltage scaling, however, presents critical problems which must be overcome. This paper reviews critical issues in mobile DRAM design and various circuit schemes to solve the problems. Focused on analog circuits, bitline sensing, IO line sensing, refresh-related schemes, DC bias generation, and schemes for higher data rate are covered.
  2. Kim, Kyung-Ki;Kim, Yong-Bin 11
    https://doi.org/10.5573/JSTS.2007.7.1.011 PDF KSCI
    This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.
  3. Lee, Jae-Seung;Bae, Jun-Hyun;Kim, Ho-Young;Um, Ji-Yong;Sim, Jae-Yoon;Park, Hong-June 20
    https://doi.org/10.5573/JSTS.2007.7.1.020 PDF KSCI
    An analytic design guide was formulated for the design of 3-stage CMOS OP amp with the nested Gm-C(NGCC) frequency compensation. The proposed design guide generates straight-forwardly the design parameters such as the W/L ratio and current of each transistor from the given design specifications, such as, gain-bandwidth, phase margin, the ratio of compensation capacitance to load capacitance. The applications of this design guide to the two cases of 10pF and 100pF load capacitances, shows that the designed OP amp work with a reasonable performance in both cases, for the range of compensation capacitance from 10% to 100% of load capacitance.
  4. Wang, I-Hsin;Liu, Shen-Iuan 28
    https://doi.org/10.5573/JSTS.2007.7.1.028 PDF KSCI
    This paper presents a high-speed flash analog-to-digital converter (ADC) for ultra wide band (UWB) receivers. In this flash ADC, the interpolating technique is adopted to reduce the number of the amplifiers and a linear and wide-bandwidth interpolating amplifier is presented. For this ADC, the transistor size for the cascaded stages is inversely scaled to improve the trade-off in bandwidth and power consumption. The active inductor peaking technique is also employed in the pre-amplifiers of comparators and the track-and-hold circuit to enhance the bandwidth. Furthermore, a digital-to-analog converter (DAC) is embedded for the sake of measurements. This chip has been fabricated in $0.13{\mu}m$ 1P8M CMOS process and the total power consumption is 113mW with 1V supply voltage. The ADC achieves 4-bit effective number of bits (ENOB) for input signal of 200MHz at 5-GSample/sec.
  5. Park, Joon-Young;Lee, Jin-Hee;Jeong, Deog-Kyoon 36
    https://doi.org/10.5573/JSTS.2007.7.1.036 PDF KSCI
    A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.
  6. Hwang, Sang-Hoon;Song, Min-Kyu 43
    https://doi.org/10.5573/JSTS.2007.7.1.043 PDF KSCI
    In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.
  7. Murugan, Balasubramanian;Saha, Samar K.;Venkat, Rama 51
    https://doi.org/10.5573/JSTS.2007.7.1.051 PDF KSCI
    This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.
  8. Ogawa, Yoshifumi;Tamura, Issei;Omura, Yasuhisa;Iida, Yukio 56
    https://doi.org/10.5573/JSTS.2007.7.1.056 PDF KSCI
    This paper describes physical meanings of various influences of cavity (or pillar) shape and filling factor of dielectric material on band structures in two-dimensional photonic crystals. Influences of circular and rectangular cross-sections of cavity (or pillar) arrays on photonic band structures are considered theoretically, and significant aspects of square and triangular lattices are compared. It is shown that both averaged dielectric constant of the photonic crystal and distribution profile of photon energy play important roles in designing optical properties. For the triangular lattice, especially, it is shown that cavity array with a rectangular cross-section breaks the band structure symmetry. So, we discuss this point from the band structure and address optical properties of lattice with a circular cross-section cavity.