JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A 3.3-V Low-Power Compact Driver for Multi-Standard Physical Layer

  • Published : 2007.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

A low-power compact driver for multistandard physical layer is presented. The proposed driver achieves low power and small area through the voltage-mode driver with trans-impedance configuration and the novel hybrid driver,. In the voltage-mode driver, a trans-impedance configuration alleviates the problem of limited common-mode range of error amplifiers and the area and power overhead due to pre-amplifier. For a standard with extended output swing, only current sources are added in parallel with the voltage-mode driver, which is named a 'hybrid driver'. The hybrid architecture not only increases output swing but reduces overall driver area. The overall driver occupies $0.14mm^2$. Power consumptions under 3.3-V supply are 24.5 mW for the voltage-mode driver and 44.5 mW for the hybrid driver.

Keywords

References

  1. P. Roo et al., 'A CMOS Transceiver Analog Front-End for Gigabit Ethernet over CAT-5 Cables,' ISSCC Dig. Tech. Papers, Feb. 2001, pp. 310-311 https://doi.org/10.1109/ISSCC.2001.912652
  2. J. Everitt et al., 'A CMOS Transceiver for 10-Mb/s and 100-Mb/s Ethernet,' IEEE J. Solid-State Circuits, Vol. 33, No. 12, pp. 2169-2177, Dec. 1998 https://doi.org/10.1109/4.735701
  3. J. N. Babanezhad, 'A 100-MHz, $50-{\Omega}$, -45-dB Distortion, 3.3-V CMOS Line Driver for Ethernet and Fast Ethernet Networking Application,' IEEE J. Solid-State circuits, Vol. 34, No.8, pp. 1044-1050, Aug. 1999 https://doi.org/10.1109/4.777101
  4. M. S. Kappes, 'A 3-V CMOS Low-Distortion Class AB Line Driver Suitable for HDSL Application,' IEEE J. Solid-State Circuits, Vol. 35, No.3, pp. 371-376, Mar. 2000 https://doi.org/10.1109/4.826819
  5. H. Khorramabadi, 'A CMOS Line Driver with 80-dB Linearity for ISDN Applications,' IEEE J. Solid-State Circuits, Vol. 27, No.4, pp. 539-544, April 1992 https://doi.org/10.1109/4.126541
  6. F. Mistlberger and R. Koch, 'Class-AB High-Swing CMOS Power Amplifier,' IEEE J. Solid-State Circuits, Vol. 27, No.7, pp. 1089-1092, July 1992 https://doi.org/10.1109/4.142606
  7. J. Kih et al., 'Class-AB Large-Swing CMOS Buffer Amplifier with Controlled Bias Current,' IEEE J. Solid-State Circuits, Vol. 28, No. 12, pp. 1350-1353, Dec. 1993 https://doi.org/10.1109/4.262009
  8. B. K. Ahuja et al., 'A Programmable CMOS Dual Channel Interface Processor for Telecommunications Applications,' IEEE J. Solid-State Circuits, Vol. SC-19, No.6, pp. 892-899, Dec. 1984 https://doi.org/10.1109/JSSC.1984.1052242