In this paper, we have analyzed the performance of a BRAM (The Broadcasting Recognizing Access Method) protocol, as a CSMA/CA (Carrier Sense Multiple Access/Collision Avoidance) scheme, which is widely used in wireles LAN systems. We have selected a Fair BRAM protocol among CSMA/CA schemes, considering the fairness of channel usage and the simplicity of the protocol. We have compared the performance of BRAM protocol to that of CSMA/CD. to research the characteristics of BRAM in wireless LAN system. In order to analyze the performance of this system, we have set up an imbedded Markov chain and calculated state transition probabilities. Then we have calculated steady state probabilities and finally derived the throughput of a Fair BRAM moder. To verify our analysis, we have simulated practical models. Then, we have found that analytic results are very close to simulation ones. Our analysis of the BRAM protocol will be expected to be very helpful to design and evaluate a MAC (Media Access Control) protocol in wireless LAN systems.

In this paper, we propose a frequency assignment algorithm to minimize intermodulation effect which is caused by nonlinear amplipification of the satellite transponder. Allmost all of the published algorithms up to now are applicable to one-level SCPC systems, the application range of those algorithms is very restricted from the viewpoint of actual practice. In this paper, we develope and propose a new frequency assignment algorithm which utilize the basic concept of Okinaka's DELINS-INSDEL algorithm to extend its applicabilty from one-level SCPC systems to multi-level systems. The proposed TDTI algorithm provides considerable generality in reducing intermodulation effect in practical satellite communication systems because of its alpplicability to multi-level and multi-bandwidth systems as well as one-level systems. Besides the TDTI algorithm which shows excellent characteristics in performance but requires somewhat long excution time. the WTDI-SDELINS algorithm is proposed in this paper to compensate TDTI's demerits in excution time. Considering the fact that there are very little published sterategies for multi-level and muti-bandwidth systems. the algorithm proposed in this paper is quite meaningful.

We analyze risks andd present the requirements of digital multisignature in electronic contract systems where several persons contract a digital document electronically. We also apply a few digital multisignature schemes that have been developed so far, to the electronic contract system and propose a new digital multisignature scheme based on the Fiat-Shamir scheme. We investigate how these schemes satisfy with the requirements and evaluate their efficiency in terms of processing speed. communication complexity, and message length Owing to the high processing speed and the high degree of satisfaction to the requirements, the proposed scheme is suitable for electronic contract systems.

In this paper, using the newly developed GaAs Schottky beam-lead diode made by Marconi company, we have developed and evaluated the waveguide type single-ended mixer at Q-band. The various components of the mixer were separately designed and optimized using the Super-Compact software. These studies included the design of the step waveguide impedance transformer and the RF-choke filter, and the optimization of a high and low impedance for the RF-choke filter. Moreover, this RF-choke filter pattern included a section to reject the second harmonic frequency of the RF signal. Finally, this Q-band mixer with 1.4GHz/400MHz IF frequency exhibits an average conversion loss of 5.3 dB over 33-50GHz bandwidth.

In this paper, waveguide banpass filters using H-plane step discontinuities are designed based on the field theory analysis and optimization of the resonator lengths as well as dimensions of discontinuities, instead of the conventional synthesis method based on the equivalent circuit. The waveguide inductive obstacles introduced by H-plane step discontinuities analyzed using mode-matching method and the generalized scattering parameters are derived. Using the derived scattering parameters of the discontinuities as well as those of resonators, waveguide bandpass filters are designed through optimization method, modified Razor search method proposed by J.H.Bandler. Using this design procedures, waveguide bandpass filters are designed and tested at X-band(center frequency 10GHz) as well as Ka-band(center frequency 35GHz).

The drain current reduction effect due to the side-gating phenomena resulted from interaction between the neighbor gates is lead to degradation of circuit performance. In this paper, these effect were modelized for circuit simulation with the shift of threshold voltage resulting from negative charge formation and the analysis of substrate leakage current resulting trapping effect. To remove dificiencies of the conventional three terminal structure, these model were implemented in SPICE with the four terminal structure, and then the constructed environment enables the simulation of circuit performance degradation resulted from side-gating effect. The validity of implemented model is proved by comparisoin with experiment data.

In this paper, we present the analytical models for substrate current and gate current of stressed SC-PMOSFET using the change of the lateral electric field distribution due to the trapped electron. Calculated Isub and Ig of stressed SC-PMOSFET agree with experimental data. Our model can be very useful explaining the logarithmic time dependence of Isub and Ig. and also the trapped electron distribution.

In this paper, we present the analytical models for the change of the lateral electric field distribution and the velocity saturation region length with the electron trapping of stressed SC-PMOSFET in the saturation region. To derive the hot-electron-induced lateral electric field of stressed SC-PMOSFET. Ko's pseudo two dimensional box model in the saturation region which illustrates the analysis of the velocity saturation region is modified under the condition of electron trapping in the oxide near the drain region. From the results, we have the following lateral electric field in the y-direction, that is, E(y) ES1satT.cosh(y/l) qNS1tT.sinh(y/l)/lCox. It is shown that the trapped electrons influence the field in the drain region. decreasing the lateral electric field. Calculated velocity saturaion length increases with the trapped electrons. increasing the drain current of stressed SCPMOSFET. This results well explain the HEIP phenomenon of PMOSFET's.

The NMOSFET with gate length of 0.1$\mu$m is fabricated by mix-and-match method. In this device, the electron beam lithography is used to form the gate layer, while other layers are formed by the stepper. The gate oxide is 7nm thick, and the device structure is normal LDD structure. The saturation Gm for gate length of 0.1$\mu$m is 246mS/mm. The subthreshold slope is 180mV/decade for 0.1$\mu$m gate length, but the slope is 80mV/decade for 0.3$\mu$m gate length.

GaAs power MESFETs with 0.8$\mu$m gate lengths are fabricated using image reversal (IR) methods on the wafer with an undoped surface layer grown by MOCVD. The fabricated GaAs power MESFETs with an undoped surface layer show that an ideality factor 1.17, a built-in potential 0.83 V, a pinch-off voltage -2.7 V, a specfic contact resistance 1.21$\times$10$^{5}$ ~3.42$\times$10$^{2}$$\Omega$-cm$^{2}$ and an extrinsic g$_{m}$ = 103.5 mS/mm. The maximum RF output power densities of the 0.8$\mu$m devices are 360 mW/mm and 499 mW/mm, and power added efficiencies 29.67% and 29.05%, for the unit gate width 150$\mu$m and 200$\mu$m at 12 GHz.

Schottky diodes have been fabricated using the SDB wafer, and their characteristics have been investigated. For comparison, conventional planar and etched most structure were made on the same substrate. The ideality factor and barrier height of the fabricated devices are found to be 1.03 and 0.77eV, respectively. Breakdown volttge of the etched mesa Schottky diode has been increased to 180V. whereas it is 90V for the planar diode. Schottky diode with an etched mesa exhibits twice improvement in breaktown voltage.

Characteristics of hot-electron-induced degradation by AC, DC was investigated for p-MOSFET's(W/L=25/l$\mu$m) with sub-10nm RTP-CVD gate oxides. It was confirmed that the surface channel p-MOSFET of a thinner gate oxide shows less degradation. Mechanisms for this effect were analyzed using a simple MOS Device degradation model. It was found that the number of generated electron traps(fixed charge) is determined by the amount of peak gate current, dependent of the gate oxide thickness, and the major cause of the smaller degradation in the thinner gate oxide devices is the lower hot electron trapping carriers.

In this paper, we present a novel scheduling algorithm using the weighted interval graph. An interval graph is constructed, where an interval is a time frame of each operation. And for each operation type, we look for the maximum clique of the interval graph: the number of nodes of the maximum clique represents the number of operation that are executed concurrently. In order to minimize resource cost. we select the operation type to reduce the number of nodes of a maximum clique. For the selected operation type, an operation selected by selection rule is moved to decrease the number of nodes of a maximum clique. A selected operation among unscheduled operations is moved repeatly and assigned to a control step consequently. The proposed algorithm is applied to the pipeline and the nonpipeline data path synthesis. The experiment for examples shows the efficiency of the proposed scheduling algorithm.

This paper, presents SECRET(SEC REliability Tool), which predicts reliability problems related to the hot-carrier and electromigration effects on the submicron MOSFETs and interconnections. To simulate DC and AC lifetime for hot-carrier damaged devices, we have developed an accurate substrate current model with the geometric sensitivity, which has been verified over the wide ranges of transistor geometries. A guideline can be provided to design hot-carrier resistant circuits by the analysis of HOREL(HOT-carrier RFsistant Logic) effect, and circuit degradation with respect to physical parameter degradation such as the threshold voltage and the mobility can also be expected. In SECRET, DC and AC MTTF values of metal lines are calculated based on lossy transmission line analysis, and parasitic resistances, inductances and capacitances of metal lines are accurately considered when they operate in the condition of high speed. Also, circuit-level reliability simulation can be applied to the determination of metal line width and-that of optimal capacitor size in substrate bias generation circuit. Experimental results obtained from the several real circuits show that SECERT is very useful to estimate and analyze reliability problems.