The radiation characteristics of a phased array antenna consisted of rectangular waveguides with a slant grid are investigated here. In particular, the effects of the slant angle on the radiation patterns are calculated by solving numerically the integral equation to the electric field over the waveguide aperture in view of the modal analysis. And it is found that the blindness on the radiation pattern can be moved by inserting a dielectric plug or sheath properly.

A concrete disign of memory circuit is presented aiming at the application of sliding diagonal test patterns. A modification of sliding diagonal test pattern includes the complexity reduction from O(n$^{32}$) to O(n) using parallel test memory concept. The control circuit design was based on delay-element, and verified via logic and circuit simulation. Area overhead was evaluated based on physical layout using a 0.7 micron design rule resulting in about 1% area increase for a typical 16Mbit DRAM.

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

Hydrogenation on the top gate and bottom gate Poly-Si TET's was performed by using Nh$_{3}$ plasma and annealing SiN film deposited by PECVD and then the electric characteristics on Poly-Si TET were investigated. As the time of NA$_{3}$ plasma treatment increaes, on/off current ratio gradually increases and the swing value decreases. The trap densities of graim boundaries in Poly-Si decrease very much during the inital 20min of hydrogenation time, and the decreasing scale becomes smaller after 20 min. The electric characteristics of the top gate TFT are better than those of the bottom gate TFT, it is considered due to the defects at the interface between the Poly-Si and the underlayer, SiO$_{2}$. After NH$_{3}$ plasma was treated for 2 hours for the top gate TFT, as the aging time atroon temperature increases on current was not scacely changed and off current decreases more than 1 order. Gate current density recovers to original value after the aging treatment for 8 days and then the electric characteristics are finally improved. It is suggested that the degraded characteristics of gate oxide are improved, from the variations of C-V characteristics with aging time. For the hydrogenation of isothermal and isochronal annealing SiN film deposited by PECVD, the characteristics of Poly-Si TFT are improved with increasing annealing temperature and are not largely changed with increasing annealing time. This results is good in agreement with the hydrogen reduction in Sin film as variations of annealing temperature and time.

Thermal behavior and $O_{2}$ plasma effects on residue and penetrated impurities formed by reactive ion etching (RIE) in CHF$_{3}$/C$_{2}$F$_{6}$ have been investigated using X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS) techniques. Decomposition of polymer residue film begins between 200-300.deg. C, and above 400.deg. C carbon compound as graphite mainly forms by in-situ resistive heating. It reveals that thermal decomposition of residue can be completed by rapid thermal anneal above 800.deg. C under nitrogen atmosphere and out-diffusion of penetrated impurities is observed. The residue layer has been removed with $O_{2}$ plasma exposure of etched silicon and its chemical bonding states have been changed into F-O, C-O etc.. And $O_{2}$ plasma exposure results in the decrease of penetrated impurities.

In an attempt to improve the electrical characteristics of tantalum pentoxide dielectric film, silicon substrate was reacted with a nitrogen plasma to form a silicon nitride of 50.angs. and then tantalum pentoxide thin films were formed by reactive sputtering in the same chamber. Breakdown field and leakage current density were measured to be 2.9 MV/cm and 9${\times}10^{8}\;A/cm^{2}$ respectively in these films whose thickness was about 180.angs.. With annealing at rectangular waveguides with a slant grid are investigated here. In particular, 900.deg. C in oxygen ambient for 100 minutes, breakdown field and leakage current density were improved to be 4.8 MV/cm and 1.61.6${\times}10^{8}\;A/cm^{2}$ respectively. It turned out that the electrical characteristics could also be improved by oxygen plasma post-treatment and the conduction mechanism at high electric field proved to be Schottky emission in these double-layered films.

기존의 알고리듬들이 완전히 검출하지 못하는 차수 2나 3의 연결된 2-결합고장을 검출하기 위하여 "알고리듬 다"가 제안되었다. 제한된 3-결합고장을 검출하는 "테스트1*", "테스트2*" 및 "알고리듬 라"가 제안되었다. "테스트1*"는 제한된 3-결합고장을 검출하는 측면에서 기존의 알고리듬들보다 시간복잡도가 감소되었다. "테스트2*" 및 "알고리듬 라"는 기존의 알고리듬들과 비교하여 시간복잡도가 감소되었고 개선된 고장 검출능력을 가진다. 그리고 요구하는 고장 검출정도에 따라 "알고리듬 라"를 순차적으로 수행시킬 수 있으며, 메모리를 병렬테스트하는 경우에 "알고리듬 라"를 수행시키면 시간복잡도가 상당히 개선된다. 비선형 번지순서를 발생시키고 두 번지부분으로 분할하여 반도체 RAM의 결합고장을 검출하는 MT(March Test)는 차수 3의 연결된 2-결합고장보다 복잡한 결합고장은 완전히 검출될 수 없다는 것이 입증되었다.

본 논문에서는 RAM에서의 functional 고장인 PSF를 검출할수 있는 "알고리듬 마"를 제안한다. 이 알고리듬은 PSF의 형태를 한정시켜서 제한된 범위의 PSF(restricted PSF or neighborhood PSF)를 검출하는 것으로써 "알고리듬 마"는 SNPSF, PNPSF 및 일부의 ANPSF를 검출하며, 고전적인 고장인 stuck-at 고장 및 천이(transition)고장도 검출한다. 이 알고리듬의 시간 복잡도는 1536xP로써 P는 메모리블럭의 분할갯수를 나타낸다. 또한 "알고리듬 마"의 BIST scheme을 제안하였다.

This paper presents a design and implementation of CAD(Computer-Aided Design) system with tools and design environments for IC(Intergrated Circuits)design. The CAD system can be easily installed in various sites with limited resources, since most CAD tools and design environments are available in the public-domain and Unix & X Window-based PC-386 and Workstation is used for the hardware platform. In order to improve the flexibility of the CAD system, objects are defined in the context of tools and environments` and object tables are programmed to describe the integration of CAD tools and design environments. During the execution, tool-objects deal with intertool communication and round-robin mechanism to incrementally control the execution of CAD tools. The IC design of LPC(Linear Predictive Coding) Speech Synthesizer is carried out to find out improvements and bugs of the CAD system.