• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.305-310
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• 2013

In this paper, the pressure sensor usable in a high temperature, using a SDB(silicon-direct-bonding) wafer of Si/$SiO_2$/Si-sub structure was provided and studied the characteristic thereof. The pressure sensor produces a piezoresistor by using a single crystal silicon as a first layer of SDB wafer, to thus provide a prominent sensitivity, and dielectrically isolates the piezoresistor from a silicon substrate by using a silicon dioxide layer as a second layer thereof, to be thus usable even under the high temperature over $120^{\circ}C$ as a limited temperature of a general silicon sensor. The measured result for a pressure sensitivity of the pressure sensor has a characteristic of high sensitivity, and its tested result for an output of the sensor further has a very prominent linearity and hysteresis characteristic.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.1092-1095
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• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.45-53
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• 1994

A new type of Si diaphragm was fabricated using Si-wafer direct bonding and two-step electrochemical etch-stopping methods. Using the new diaphragm structure in mechanical sensors, more precise control of cavity depth and diaphragm thickness was achievable. Also, the propagation of the stress, which was generated near the bonding interface, to the surface can be avoided. Finally, a piezoresistive-type Si pressure sensor was fabricated utilizing the diaphragm and a digital pressure gauge, which can display units of pressure, was realized.

• Journal of the Korean Vacuum Society
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• v.13 no.1
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• pp.1-8
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• 2004

The SOI wafer fabrication technique has been developed by using ion-cut process, based on proton implantation and wafer bonding techniques. It has been shown by TRIM simulation that 65 keV proton implantation is required for the standard SOI wafer (200 nm SOI, 400 nm BOX) fabrication. In order to investigate the optimum proton dose and primary annealing condition for wafer splitting, the surface morphologic change has been observed such as blistering and flaking. As a result, effective dose is found to be in the 6∼$9\times10^{16}$ $H^{+}/\textrm{cm}^2$ range, and the annealing at $550^{\circ}C$ for 30 minutes is expected to be optimum for wafer splitting. The depth distribution of implanted hydrogen has been experimentally confirmed by ERD and SIMS measurements. The microstructure evolution in the damaged layer was also studied by X-TEM analysis.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.38-41
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• 2001

In this work, we have been studied the characteristics of each nitride film for the optimization of PMD(pre-metal dielectric) liner nitride process, which can applicable in the recent semiconductor manufacturing process. The deposition conditions of nitride film were splited by PO (protect overcoat) nitride, baseline, low hydrogen, high stress and low hydrogen, respectively. And also we tried to catch hold of correlation between BPSG(boro-phospho silicate glass) deposition and densification. Especially, we used FTIR area method for the analysis of density change of Si-H bonding and Si-NH-Si bonding, which decides the characteristics of nitride film. To judge whether the deposited films were safe or not, we investigated the crack generation of wafer edge after BPSG densification, and the changes of nitride film stress as a function of RF power variation.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.206-210
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• 2005

The SOI structure with buried alumina was fabricated by ALD followed by bonding and etchback process. The interface of alumina and silicon was analyzed by CV measurements and cross section was investigated by SEM analysis. The density of interface state of alumina and silicon was 2.5E11/$cm^{2}$-eV after high temperature annealing for wafer bonding. It was confirmed that the surface silicon layer was completely isolated from substrate by cross section SEM and AES depth profile. The device on this alumina SOI structure would have better thermal properties than that on conventional SOI due to higher thermal conductivity of alumina than that of silicon dioxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.95-100
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• 2006

The GaAs-on-insulator (GOI) wafer fabrication technique has been developed by using ion-cut process, based on hydrogen ion implantation and wafer direct bonding techniques. The hydrogen ion implantation condition for the ion-cut process in GaAs and the associated implantation mechanism have been investigated in this paper. Depth distribution of hydrogen atoms and the corresponding lattice disorder in (100) GaAs wafers produced by 40 keV hydrogen ion implantation were studied by SIMS and RBS/channeling analysis, respectively. In addition, the formation of platelets in the as-implanted GaAs and their microscopic evolution with annealing in the damaged layer was also studied by cross-sectional TEM analysis. The influence of the ion fluence, the implantation temperature and subsequent annealing on blistering and/or flaking was studied, and the optimum conditions for achieving blistering/splitting only after post-implantation annealing were determined. It was found that the new optimum implant temperature window for the GaAs ion-cut lie in $120{\sim}160^{\circ}C$, which is markedly lower than the previously reported window probably due to the inaccuracy in temperature measurement in most of the other implanters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.13-20
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• 2008

This paper describes the methods of spacer-fabrication for wafer-level CIS(CMOS Image Sensor) assembly. We propose three methods using SU-8, PDMS and Si-interposer for the spacer-fabrication. For SU-8 spacer, novel wafer rotating system is developed and for PDMS(poly-dimethyl siloxane) spacer, new fabrication-method is used to bond with alignment of glass/PDMS/glass structure. And for Si-interposer, DFR(Dry Film Resist) is used as adhesive layer. The spacer using Si-interposer has the strongest bonding strength and the strength is 32.3MPa with shear.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3_1spc
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• Transactions of the Society of Information Storage Systems
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• v.2 no.3
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• pp.163-168
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• 2006

Small form factor optical pickup (SFFOP) corresponding to BD specifications is strongly proposed for the next-generation portable storage device. In order to generate SFFOP, small sized optical pickup has been fabricated. We have developed a small sited optical pickup that is called the integrated optical pickup (IOP). The fabrication method of this system is mainly dependant on the use of the wafer based micro fabrication technology, which has been used in MEMS process such as photolithography, reactive ion etching, wafer bonding, and packaging process. This approach has the merits for mass production and high assembling accuracy. In this study, to generate the small sized optical pickup for high recording capacity, IOP corresponding to BD specifications has been designed and developed, including three main parts, 1) design, fabrication and evaluation of objective lens unit, 2) design and fabrication of IOP and 3) evaluation process of FES and TES.