• Journal of the Microelectronics and Packaging Society
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• v.31 no.2
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• pp.1-8
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• 2024

Bonding wires are composed of conductive metals of Au, Ag & Cu with excellent electrical conductivities for transmitting power and signals to wafer chips. Wire metals do not provide electrical insulation, adhesion promoter and corrosion passivation. Adhesion between metal wires is extremely weak, which is responsible for wire cut failures during thermal cycling. Organic coating for electrical insulation does not satisfy bondability and manufacturability, and it is complex to apply very thin organic coating on metal wires. Automotive packages require enhanced reliability of packages under harsh conditions. LED and power packages are susceptible to wire cut failures. Contrary to conventional OCB behaviors, forming gas was not required for free air ball formation for both Ag and Pd-coated Cu wires with Al₂O₃ passivation.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.79-83
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• 2007

We have developed a compact and cost-effective camera module on the basis of wafer-scale replication technology. A multiple-layered structure of several aspheric lenses in a mobile camera module is first assembled by bonding multiple glass-wafers on which 2-dimensional replica arrays of identical aspheric lenses are UV-embossed, followed by dicing the stacked wafers and packaging them with image sensor chips. We have demonstrated a VGA camera module fabricated by the wafer-scale replication processing with various UV-curable polymers having refractive indices between 1.4 and 1.6, and with three different glass-wafers of which both surfaces are embossed as aspheric lenses having 200 um sag-height and aspheric-coefficients of lens polynomials up to tenth-order. We have found that precise compensation in material shrinkage of the polymer materials is one of the most technical challenges, in order to achieve a higher resolution in wafer-scaled lenses for mobile camera modules.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.29-33
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• 2010

Among several critical topics in semiconductor fabrication technology, particles in addition to bonded surface contaminations are issues of great concerns. This study reports the development of a system which inspects wafer bond integrity by analyzing laser beam transmittance deviations and the variations of the intensity caused by the defect thickness. Since the speckling phenomenon exists inherently as long as the laser is used as an optical source and it degrades the inspection accuracy, speckle contrast is another obstacle to be conquered in this system. Consequently speckle contrast reduction methods were reviewed and among the all remedies have been established in the past 30 years the most adaptable solution for inline inspection system is applied. Simulation and subsequently design of experiments has been utilized to discover the best solution to improve irradiance distribution and detection accuracy. Comparison between simulation and experimental results has been done and it confirms an outstanding detection accuracy achievement. Bonded wafer inspection system has been developed and it is ready to be implemented in FAB in the near future.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.57-64
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology fur their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electrodes nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.137-140
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• 2014

With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300 mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.

• Journal of Powder Materials
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• v.28 no.1
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• pp.25-30
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• 2021

The surface of silicon dummy wafers is contaminated with metallic impurities owing to the reaction with and adhesion of chemicals during the oxidation process. These metallic impurities negatively affect the device performance, reliability, and yield. To solve this problem, a wafer-cleaning process that removes metallic impurities is essential. RCA (Radio Corporation of America) cleaning is commonly used, but there are problems such as increased surface roughness and formation of metal hydroxides. Herein, we attempt to use a chelating agent (EDTA) to reduce the surface roughness, improve the stability of cleaning solutions, and prevent the re-adsorption of impurities. The bonding between the cleaning solution and metal powder is analyzed by referring to the Pourbaix diagram. The changes in the ionic conductivity, H2O2 decomposition behavior, and degree of dissolution are checked with a conductivity meter, and the changes in the absorbance and particle size before and after the reaction are confirmed by ultraviolet-visible spectroscopy (UV-vis) and dynamic light scattering (DLS) analyses. Thus, the addition of a chelating agent prevents the decomposition of H2O2 and improves the life of the silicon wafer cleaning solution, allowing it to react smoothly with metallic impurities.

• Korean Journal of Materials Research
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• v.18 no.4
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• pp.204-210
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• 2008

$1.5\;{\mu}m$-thick copper films deposited on silicon wafers were successfully bonded at $415^{\circ}C$/25 kN for 40 minutes in a thermo-compression bonding method that did not involve a pre-cleaning or pre-annealing process. The original copper bonding interface disappeared and showed a homogeneous microstructure with few voids at the original bonding interface. Quantitative interfacial adhesion energies were greater than $10.4\;J/m^2$ as measured via a four-point bending test. Post-bonding annealing at a temperature that was less than $300^{\circ}C$ had only a slight effect on the bonding energy, whereas an oxygen environment significantly deteriorated the bonding energy over $400^{\circ}C$. This was most likely due to the fast growth of brittle interfacial oxides. Therefore, the annealing environment and temperature conditions greatly affect the interfacial bonding energy and reliability in Cu-Cu bonded wafer stacks.

• International Journal of Quality Innovation
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• v.8 no.3
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• pp.81-112
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• 2007

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five-point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.3
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• pp.1-6
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• 2016

The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.