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Characterization of Backside Passivation Process for Through Silicon via Wafer

TSV 웨이퍼 공정용 Si3N4 후막 스트레스에 대한 공정특성 분석

  • Kang, Dong Hyun (Department of Electronic Engineering, Myongji University) ;
  • Gu, Jung Mo (Department of Electronic Engineering, Myongji University) ;
  • Ko, Young-Don (Department of Mechanical and Industrial Engineering, University of Toronto) ;
  • Hong, Sang Jeen (Department of Electronic Engineering, Myongji University)
  • 강동현 (명지대학교 전자공학과) ;
  • 구중모 (명지대학교 전자공학과) ;
  • 고영돈 (토론토대학교 기계&산업공학과) ;
  • 홍상진 (명지대학교 전자공학과)
  • Received : 2013.12.30
  • Accepted : 2014.02.11
  • Published : 2014.03.01

Abstract

With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300 mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.

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References

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