• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.71-74
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• 2019

In this study, we fabricated two standard and inverted quantum dot light emitting diodes (QLEDs) using $TiO_2$ nanoparticles (NPs) with lower electron mobility than ZnO NPs as inorganic electron transport layer to suppress electron injection into the emitting layer. Current density was much higher for the inverted QLEDs than the standard ones. The inverted QLEDs were brighter, but showed low current efficiency due to the high current density. In addition, as the current density was higher, the driving voltage was higher, and the red shift was confirmed in the emission wavelength spectrum. The low current density in the standard structured devices showed that the possibility that $TiO_2$ NPs could suppress the electron injection in the QLEDs.

• Journal of the Korean Society of Radiology
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• v.11 no.7
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• pp.663-669
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• 2017

In diagnostic medical imaging, it is essential to reduce the scattered radiation for the high medical image quality and low patient dose. Therefore, in this study, the influence of the scattered radiation on medical images was analyzed as the tube voltage increases. For this purpose, ANSI chest phantom was used to measure the scattering ratio, and the scattering effect on the image quality was investigated by RMS evaluation, RSD and NPS analysis. It was found that the scattering ratio with increasing x-ray tube voltage gradually increased to 48.8% at 73 kV tube voltage and to 80.1% at 93 kV tube voltage. As a result of RMS analysis for evaluating the image quality, RMS value according to increase of tube voltage was increased, resulting in low image quality. Also, the NPS value at 2.5 lp/mm spatial frequency was increased by 20% when the tube voltage was increased by 93 kV compared to the tube voltage of 73 kV. From this study, it can be seen that the scattering radiation have a significant effect on the image quality according to the increase of x-ray tube voltage. The results of this study can be used as basic data for the improvement of medical imaging quality.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.9-17
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• 2006

We proposed a new High-speed CMOS Level Up/Down Shifter circuits that can be used with Dynamic Voltage and Frequency Scaling(DVFS) algorithm, for low power system in the SoC(System-on-Chip). This circuit used to interface between the other voltage levels in each CMOS circuit boundary, or between multiple core voltage levels in a system bus. Proposed circuit have advantage that decrease speed attenuation and duty ratio distortion problems for interface. The level up/down shifter of the proposed circuit designed that operated from multi core voltages$(0.6\sim1.6V)$ to used voltage level for each IP at the 500MHz input frequency The proposed circuit supports level up shifting from the input voltage levels, that are standard I/O voltages 1.8V, 2.5V, 3.3V, to multiple core voltage levels in between of $0.6V\sim1.6V$, that are used internally in the system. And level down shifter reverse operated at 1Ghz input frequency for same condition. Simulations results are shown to verify the proposed function by Hspice simulation, with $0.6V\sim1.6V$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process and $0.65{\mu}m$ CMOS model parameters. Moreover, it is researched delay time, power dissipation and duty ration distortion of the output voltage witch is proportional to the operating frequency for the proposed circuit.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of Sensor Science and Technology
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• v.7 no.6
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• pp.401-408
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• 1998

A dual-channel automatic ac-dc voltage transfer error measurement system in which the output voltages of two thermal voltage converters which are ac voltage standard are directly measured at the same time to reduce the output voltage drift is described. Forward-reverse measurement method by using a two-channel scanner is used to cancel the offset voltage of the voltmeters. The agreements of the 4-V TVC comparison results between other national standards institute and Korea Research Institute of Standards and Science were less than about ${\pm}2\;ppm$ in the frequency range of $40\;Hz{\sim}100\;kHz$, and were less than about ${\pm}4\;ppm$ at $200\;kHz{\sim}1\;MHz$. Measurement uncertainty is reduced significantly from ${\pm}4\;ppm$ of manual system to ${\pm}3\;ppm$ of new system(up to 100 kHz) typically and great increase in comparison efficiency has been achieved by this system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.635-640
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• 2016

This paper dealt with the deterioration characteristics and an on-line diagnosis equipment for SPDs (surge protective devices). An accelerated aging test was carried out using a $8/20{\mu}s$ standard lightning impulse current to analyze the changes of electrical characteristics and to propose the diagnostic parameters and the criterion for deterioration of ZnO varistor which is the core component of SPDs. Based on the experimental results, an on-line diagnosis equipment for SPD was fabricated, which can measure the total leakage current, reference and clamping voltage. The leakage current measurement circuit was designed using a low-noise amplifier and a clamp type ZCT. A linear controller, the leakage current measurement part and a HVDC were used in the measurement of reference voltage. The measurement circuit of clamping voltage consisted of a surge generator and a coupling circuit. In a calibration process, measurement error of the prototype equipment was less than 3%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.2
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• pp.190-197
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• 2002

In this thesis, ZnO varistors with various formulation, such as A∼E, were fabricated according to ceramic fabrication method. The microstructure, electrical properties, and surge characteristics of ZnO varistors were investigated according to ZnO varistors with various formulation. In the microstructure, A∼E\`s ZnO varistor ceramics sintered at 1130$\^{C}$ was consisted of ZnO grain(ZnO), spinel phase (Zn$\_$2.33/Sb$\_$0.67/O$\_$4/), Bi-rich phase(Bi$_2$O$_3$) and intergranuler phase, wholly. Lightning impulse residual voltage of A, B, C and E\`s ZnO varistors suited standard characteristics, below 12kV at current of 5kA. On the contrary, D\`s ZnO varistor exhibited high residual voltage as high reference voltage. In the accelerated aging test, leakage current and watt loss of B, C and D\`s ZnO varistors increases abruptly with stress time under the first a.c. stress(115$\^{C}$/3.213kV/300h). Consequently, C varistor exhibited a thermal run away. On the contrary, leakage current and watt loss of A and C\`s ZnO varistors which show low initial leakage current exhibited constant characteristics. After high current impulse test, A\`s ZnO varistor has broken the side of varistor but impulse current flowed. On the contrary, E\`s ZnO Varistor exhibited good discharge characteristics which the appearance of varistor was not wrong such as puncture, flashover, creaking and other significant damage. After long duration impulse current test, E\`s ZnO varistor exhibited good discharge characteristics which the appearance of varistor was not wrong such as puncture, flashover, creaking and other significant damage. After high current impulse test and long duration impulse current test, E\`s ZnO varistor exhibited very good characteristics which variation rate of residual voltage is 1.4% before and after test.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.212-215
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• 2016

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.30-37
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• 1998

An analog array with a 1.2 $\mu\textrm{m}$ double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Journal of IKEEE
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• v.14 no.2
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• pp.82-89
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• 2010

In this paper, a buck-boost converter using three DTMOS(Dynamic Threshold Voltage MOSFET) switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. DTMOS with low on-resistance is designed to decrease conduction loss. The threshold voltage of DTMOS drops as the gate voltage increases, resulting in a much higher current handling capability than standard MOSFET. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.2MHz oscillation frequency, and maximum efficiency 90%. Moreover, the LDO(low drop-out) is designed to increase the converting efficiency at the standby mode below 1mA.