• Title/Summary/Keyword: top gate

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Electrical Coupling of Monolithic 3D Inverter Consisting of Junctionless FET (Junctionless FET로 구성된 적층형 3차원 인버터의 전기적 상호작용에 대한 연구)

  • Jang, Ho-Yeong;Kim, Kyung-won;Ahn, Tae-Jun;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.614-615
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    • 2016
  • I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.

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Investigation of Electrical Coupling Effect by Random Dopant Fluctuation of Monolithic 3D Inverter (Monolithic 3D Inverter의 RDF에 의한 전기적 커플링 영향 조사)

  • Lee, Geun Jae;Yu, Yun Seop
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.05a
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    • pp.481-482
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    • 2022
  • In this paper, effect of random dopant fluctuation (RDF) of the top-transistor in a monolithic 3D inverter composed of MOSFET transistors is investigated with 3D TCAD simulation when the gate voltage of the bottom-transistor is changed. The sampling for investigating RDF effect was conducted through the kinetic monte carlo method, and the RDF effect on the threshold voltage variation in the top-transistor was investigated, and the electrical coupling between top-transistors and bottom-transistors was investigated.

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Analysis of Subthreshold Swing for Ratio of Channel Length and Thickness of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET의 채널길이와 두께 비에 따른 문턱전압이하 스윙 분석)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.3
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    • pp.581-586
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    • 2015
  • This paper has analyzed the variation of subthreshold swing for the ratio of channel length and thickness for asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factors to control the short channel effects increase since top and bottom gate structure can be fabricated differently. The degradation of transport property due to rapid increase of subthreshold swing can be specially reduced in the case of reduction of channel length. However, channel thickness has to be reduced for decrease of channel length from scaling theory. The ratio of channel length vs. thickness becomes the most important factor to determine subthreshold swing. To analyze hermeneutically subthreshold swing, the analytical potential distribution is derived from Poisson's equation, and conduction path and subthreshold swing are calculated for various channel length and thickness. As a result, we know conduction path and subthreshold swing are changed for the ratio of channel length vs. thickness.

Electrical transport characteristics of deoxyribonucleic acid conjugated graphene field-effect transistors

  • Hwang, J.S.;Kim, H.T.;Lee, J.H.;Whang, D.;Hwang, S.W.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.482-483
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    • 2011
  • Graphene is a good candidate for the future nano-electronic materials because it has excellent conductivity, mobility, transparency, flexibility and others. Until now, most graphene researches are focused on the nano electronic device applications, however, biological application of graphene has been relatively less reported. We have fabricated a deoxyribonucleic acid (DNA) conjugated graphene field-effect transistor (FET) and measured the electrical transport characteristics. We have used graphene sheets grown on Ni substrates by chemical vapour deposition. The Raman spectra of graphene sheets indicate high quality and only a few number of layers. The synthesized graphene is transferred on top of the substrate with pre-patterned electrodes by the floating-and-scooping method [1]. Then we applied adhesive tapes on the surface of the graphene to define graphene flakes of a few micron sizes near the electrodes. The current-voltage characteristic of the graphene layer before stripping shows linear zero gate bias conductance and no gate operation. After stripping, the zero gate bias conductance of the device is reduced and clear gate operation is observed. The change of FET characteristics before and after stripping is due to the formation of a micron size graphene flake. After combined with 30 base pairs single-stranded poly(dT) DNA molecules, the conductance and gate operation of the graphene flake FETs become slightly smaller than that of the pristine ones. It is considered that DNA is to be stably binding to the graphene layer due to the ${\pi}-{\pi}$ stacking interaction between nucleic bases and the surface of graphene. And this binding can modulate the electrical transport properties of graphene FETs. We also calculate the field-effect mobility of pristine and DNA conjugated graphene FET devices.

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An Organic Electrophosphorescent Device Driven by All-Organic Thin-Film Transistor using Polymeric Gate Insulator

  • Pyo, S.W.;Shim, J.H.;Kim, Y.K.
    • Journal of Information Display
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    • v.4 no.2
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    • pp.1-6
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    • 2003
  • In this paper, we demonstrate that the organic electrophosphorescent device is driven by the organic thin film transistor with spin-coated photoacryl gate insulator. It was found that electrical output characteristics in our organic thin film transistors using the staggered-inverted top-contact structure showed the non-saturated slope in the saturation region and the sub-threshold nonlinearity in the triode region, where we obtained the maximum power luminance that was about 90 $cd/m^2$. Field effect mobility, threshold voltage, and on-off current ratio in 0.45 ${\mu}m$ thick gate dielectric layer were 0.17 $cm^2/Vs$, -7 V, and $10^6$ , respectively. In order to form polyimide as a gate insulator, vapor deposition polymerization process was also introduced instead of spin-coating process, where polyimide film was co-deposited by high-vacuum thermal evaporation from 4,4'-oxydiphthalic anhydride (ODPA) and 4,4'-oxydianiline (ODA) and cured at 150${\sqsubset}$for 1hr. It was also found that field effect mobility, threshold voltage, on-off current ratio, and sub-threshold slope with 0.45 ${\mu}m$ thick gate dielectric films were 0.134 $cm^2/Vs$, -7 V, and $10^6$ A/A, and 1 V/decade, respectively.

Drain Induced Barrier Lowering of Asymmetric Double Gate MOSFET for Channel Doping Profile (비대칭 DGMOSFET의 도핑분포함수에 따른 DIBL)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2643-2648
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    • 2015
  • This paper analyzes the phenomenon of drain induced barrier lowering(DIBL) for doping profiles in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to the change of doping profile to influence on potential distribution. As a results, the DIBL is significantly influenced by projected range and standard projected deviation, the variables of channel doping profiles. The change of DIBL shows greatly in the range of high doping concentration such as $10^{18}/cm^3$. The DIBL increases with decrease of channel length and increase of channel thickness, and with increase of bottom gate voltage and top/bottom gate oxide film thickness.

Relation of Conduction Path and Subthreshold Swing for Doping Profile of Asymmetric Double Gate MOSFET (비대칭 DGMOSFET의 도핑분포함수에 따른 전도중심과 문턱전압이하 스윙의 관계)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.8
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    • pp.1925-1930
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    • 2014
  • This paper has analyzed the relation of conduction path and subthreshold swing for doping profile in channel of asymmetric double gate(DG) MOSFET. Since the channel size of asymmetric DGMOSFET is greatly small and number of impurity is few, the high doping channel is analyzed. The analytical potential distribution is derived from Possion's equation, and Gaussian distribution function is used as doping profile. The conduction path and subthreshold swing are derived from this analytical potential distribution, and those are investigated for variables of doping profile, projected range and standard projected deviation, according to the change of channel length and thickness. As a result, subthreshold swing is reduced when conduction path is approaching to top gate, and that is increased with a decrease of channel length and a increase of channel thickness due to short channel effects.

Improvement of carrier transport in silicon MOSFETs by using h-BN decorated dielectric

  • Liu, Xiaochi;Hwang, Euyheon;Yoo, Won Jong
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2013.05a
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    • pp.97-97
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    • 2013
  • We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

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PLS-II separator the vacuum electron gun beam current emission test (PLS-II 전자총 진공이원화와 빔 전류 인출시험)

  • Son, Yoon-Kyoo
    • Proceedings of the KIEE Conference
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    • 2011.07a
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    • pp.1580-1581
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    • 2011
  • The linear accelerator of Pohang Accelerator Laboratory(PAL) will drive a top-up mode operation in PLS-II(Pohang Light Source-II). Due to this kind of the operation mode, the electron gun is expected to have shorter life time of the cathode. Further in the PLS-II, two gate valves will be installed in front of the electron gun. The distance between the pre-bunching section and the electron gun will increase by 400 mm compared to the existing system due to the insertion of these gate valves. As a result the incident electron beam. One of the goals to improve the beam pulse width is by incorporating suitable biased voltage. In this paper, we will present test results of beam pulse width as a function of different biased voltage and focusing solenoid coil.

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Electrical Effects of the Adhesion Layer Using the VDP Process on Dielectric

  • Lee, Dong-Hyun;Pyo, Sang-Woo;Hyung, Gun Woo;Kim, Young-Kwan
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1313-1316
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    • 2005
  • In the present paper, it was investigated that adhesion layer on gate insulator could affect the electrical characteristics for the organic thin film transistors (OTFTs). The polyimide (PI) as organic adhesion layer was fabricated by using the vapor deposition polymerization (VDP) processing . It was found that electrical characteristics improved comparing OTFTs using adhesion layer to another. We researched adhesion layer as a function of thickness. For inverted-staggered top contact structure, field effect mobility, threshold voltage, and on-off current ratio of OTFTs using adhesion layer of PI 15 nm thickness on the gate insulator with a thickness of 0.2 ${\mu}m$ were about 0.5 $cm^2/Vs$, -0.8 V, and $10^6$, respectively.

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