• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.1-9
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• 2001

In the APON(ATM Passive Optical Network), the transmission of the upstream traffic is based on a TDMA(Time Division Multiple Access) method that an OLT(Optical Line Termination) permits ONUs(Optical Network Units) sending cells by allocating time slots. Because the upstream is not a streaming mode, the cell synchronizer has to be operated in the burst mode. Also, the cell phase monitor is required to prevent collisions between cells which are transmitted by multiple ONUs through a single optical fiber. In this paper, a TDMA burst cell synchroniser is implemented with the FPGA(Field Programmable Gate Array) being used in the APON based on G.983.1 for transmitting upstream cells. It has two main functions which are the upstream data recovery and the phase monitoring. The former is to recover the upstream data and clock in the OLT by seeking the preamble which is the overhead of the upstream time slot and by aligning the phase of the bit and cell with the system clock. The latter is to provide the information to the ONU to compensate for the equalization delay by monitoring continuously the phase difference between adjacent cells to avoid the cell collision on the upstream.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.6
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• pp.460-469
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• 2015

This study's aim is for reducing big data transfer time of IoT healthcare devices by modulating digital bits into Manchester code including zero-voltage idle as information for secondary compressed binary cluster's compartment after two step compression of compressing binary data into primary and secondary binary compressed clusters for each binary clusters having compression benefit of 1 bit or 2 bits. Also this study proposed that as department information of compressed binary clusters, inserting idle signal into Manchester code will have benefit of reducing transfer time in case of compressing binary cluster into secondary compressed binary cluster by 2 bits, because in spite of cost of 1 clock idle, another 1 bit benefit can play a role of reducing 1 clock transfer time. Idle signal is also never consecutive because the signal is for compartment information between two adjacent secondary compressed binary cluster. Voltage transition on basic rule of Manchester code is remaining while inserting idle signal, so DC balance can be guaranteed. This study's simulation result said that even compressed binary data by another compression algorithms could be transferred faster by as much as about 12.6 percents if using this method.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.5
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• pp.93-101
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• 2008

Side channel attacks are well known as one of the most powerful physical attacks against low-power cryptographic devices and do not take into account of the target's theoretical security. As an important succeeding factor in side channel attacks (specifically in DPAs), exact time-axis alignment methods are used to overcome misalignments caused by trigger jittering, noise and even some countermeasures intentionally applied to defend against side channel attacks such as random clock generation. However, the currently existing alignment methods consider only on the position of signals on time-axis, which is ineffective for certain countermeasures based on time-axis misalignments. This paper proposes a new signal alignment method based on interpolation and decimation techniques. Our proposal can align the size as well as the signals' position on time-axis. The validity of our proposed method is then evaluated experimentally with a smart card chip, and the results demonstrated that the proposed method is more efficient than the existing alignment methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.5
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• pp.677-684
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• 2021

This paper presents a time-to-digital converter for measuring absolute time differences. The time-to-digital converter was designed and fabricated in 0.18-um CMOS technology and it can be applied to Light Detection and Ranging system which requires long time-cover range and 50ps time resolution. Since designed time-to-digital converter adopted the reference clock of 625MHz generated by phase locked loop, it could have absolute time resolution of 50ps after automatic calibration and its cover range was over than 800ns. The time-to-digital converter adopted a counter and chain delay lines for time measurement. The counter is used for coarse time measurement and chain delay lines are used for fine time measurement. From many times experiments, fabricated time-to-digital converter has 50 ps time resolution with maximum INL of 0.8 LSB and its power consumption is about 70 mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1083-1091
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• 2017

This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat's little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Animal cells and systems
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• v.6 no.3
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• pp.239-245
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• 2002

Plasma melatonin, thyroid-stimulating hormone (TSH) and body temperature were measured simultaneously and continuously before and after the sleep-wake cycle was shifted in 4 healthy males and changes in the circadian rhythm itself and in the phase relationship among these circadian rhythms were determined. Normal sleep-wake cycle (sleep hours: 2300-0700) was delayed by 10 h (sleep hours: 0900-1700) during the experiment. Even after this shift the typical melatonin rhythm was maintained: low during daytime and high during night. The melatonin rhythm was gradually delayed day by day. The TSH rhythm was also maintained fundamentally during 3 consecutive days of altered sleep-wake cycle. The phase was also delayed gradually but remarkably. The daily rhythm of body temperature was changed by the alteration of sleep-wake cycle. The body temperature began to decrease at the similar clock time as in the control but the decline during night awake period was less steep and the lowered body temperature persisted during sleep. The hormonal profiles during the days of shifted sleep/wake cycle suggest that plasma melatonin and TSH rhythms are basically regulated by an endogenous biological clock. The parallel phase shift of melatonin and TSH upon the change in sleep-wake cycle suggests that a common unitary pacemaker probably regulates these two rhythms. The reversal phase relationship between body temperature and melatonin suggests that melatonin may have a hypothermic effect on body temperature. The altered body temperature rhythm suggests that the awake status during night may inhibit the circadian decrease in body temperature and that sleep sustains the lowered body temperature. It is probable but uncertain that there ave causal relationships among sleep, melatonin, TSH, and body temperature.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Korean Journal of Optics and Photonics
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• v.13 no.4
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• pp.295-300
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• 2002

We developed an optical transmitter and receiver for an electrical time division multiplexed (ETDM) 20 Gb/s optical transmission system, and experimentally investigated their characteristics. Especially, the clock extraction circuit, which is a key component in realizing broadband optical transmission receivers, was realized by using an NRZ-to-PRZ converter implemented with a half-period delay line and an EX-OR, a high-Q bandpass filter using a cylindrical dielectric resonator, and a microstrip coupled-line bandpass filter. Finally, the bit-error-rate of demultiplexed 10 Gb/s electrical signal after back to-back transmission was measured, and a high receiver sensitivity [-26.2 dBm for NRZ ($2^{7}-1$) pseudorandom binary sequence (PRBS)] was obtained

• Journal of the Korean Institute of Navigation
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• v.14 no.2
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• pp.1-14
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• 1990

The Radio Navigation System(R. N. S.) has been progressed consistantly with the development of electric-electronic engineering techniques since the R. D. E had been developed in 1910. The R. N. S. mostly depends on either Hyperbolic Navigation System(H. N. S.) or Spherical Navigation System(S. N. S.) in the ocean, and on Rectangular Navigation System (R. N. S.) in the air near the airport or an a combinations of the above systems in both area. Another effective R. N. S may be the Ellipse-Hyperbola Navigation System(E-H N. S.), which is proposed and named such in this paper. The equations calculating GDOP are derived and the GDOP values are calculated in the case of H. N. S., S. N. S, and E-H. N. S., respectively, for the specified case that four transmitting stations are arranged on the apex of a square, Then the GDOP diagrams of above navigation systems are presented for qualitative comparison in this paper. To measure the distances from the receiver to the stations in S. N. S., and/or the sum of distances to two stations in E-H N. S., the time synchronization between the transmitter clocks and the receiver clock is a major premise. The author has proposed the algorithm for getting this synchronmization utilizing the by S. N. S. or E-H N. S while GDOPs of those are relatively good. Even though clock synchronization error is a voidable due to the fix error used, the simulated results shows that the position accuracy of S. N. S. and E-H N. S. by the proposed method is far upgraded compared with that determined by H. N. S. directly, as far as the outer region of transmitter arrangement is concerned.