1 |
D. W. Boerstler, 'A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz,' IEEE JSSC, Vol. 34, No. 4, pp.513-519, Apr. 1999
|
2 |
Henrik O. Johansson, 'A Simple Precharged CMOS Phase Frequency Detector,' IEEE JSSC, Vol. 33, No. 2, pp. 295-299, Feb. 1998
|
3 |
Tae-Hun Kim and Beomsup Kim, 'Dual-loop Digital for Adaptive Clock Recovery,' in Proc. IEEE JSSC, Vol. 4, pp. 410-414, July 1999
|
4 |
W. Rhee, 'Design of Low-Jitter 1-GHZ Phase-Locked Loops for Digital Clock Generation,' in Proc. IEEE Sympo. on Cir. and Sys, Vol. 2, pp. 520-523, May 1999
|
5 |
Kyoohyun Lim et al, 'A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization,' IEEE JSSC, Vol. 35, No. 6, pp. 807-815, June 2000
|
6 |
B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits : Theory and Design, IEEE Press, 1996
|
7 |
Sungjoon Kim et al., 'A 960Mbps/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,' IEEE JSSC, Vol. 32, No.5, pp.691-699, May 1997
|
8 |
Jung-Dong Cho, et al., 'A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops,' IEICE Trans. Fundamentals, Vol. E82-A, No. 11, pp. 2514-2520, Nov. 1999
|