A High Speed and Low Jitter PLL Clock generator

고속 저잡음 PLL 클럭 발생기

  • 조정환 (金浦大學 電子情報系列) ;
  • 정정화 (漢陽大學校 電子電氣컴퓨터工學部)
  • Published : 2002.09.01

Abstract

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

본 논문에서는 다중 PFD(Phase Frequency Detector)와 적응 전하펌프 회로를 설계하여 지터 잡음 특성과 주파수 획득 과정을 향상시킨 새로운 PLL 클럭 발생기를 제안한다. 기존의 PLL은 넓은 데드존과 듀티 사이클 특성을 갖고 있기 때문에 지터잡음을 발생하고, 긴 지연시간 때문에 고속 동작에는 부적합하다. 본 논문에서는 이러한 문제를 해결하기 위하여, TSPC(True Single Phase Clocking) 회로를 이용하여 다중 구조를 갖는 PFD를 설계하였다. 데드존 특성, 듀티 사이클의 제한조건을 개선할 수 있도록 회로를 설계하였으며, 탁월한 지터잡음 성능을 향상시킬 수 있었다. 또한 적응 전하펌프 회로를 사용하여 PLL을 설계하였으며 루프필터의 전하펌프 전류를 증가시킴으로써 주파수 획득 특성을 개선 할 수 있었다. Hspice 시뮬레이션을 수행한 결과, 제안한 PLL은 데드존이 0.01ns 미만이고, 입력신호의 듀티 사이클에 무관하며, 50ns의 빠른 획득시간을 갖는 것을 확인할 수 있었다. 따라서 제안된 회로는 고성능 마이크로프로세서 및 디지털시스템에 적용될 수 있다.

Keywords

References

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